Lines Matching +full:tx +full:- +full:sync +full:- +full:mode
4 * SPDX-License-Identifier: Apache-2.0
7 * https://github.com/Decawave/mynewt-dw1000-core.git
14 * Copyright (C) 2017-2018, Decawave Limited, All Rights Reserved
24 * http://www.apache.org/licenses/LICENSE-2.0
75 /* Frame Filtering Behave as a Co-ordinator */
106 /* Standard Frame mode */
108 /* Long Frames mode */
110 /* Disable Smart TX Power control */
112 /* Receiver Mode 110 kbps data rate */
117 * Receiver Auto-Re-enable.
118 * This bit is used to cause the receiver to re-enable automatically
126 /* System Time Counter (40-bit) */
180 * of non-standard values
203 /* Bit mask to access Transmit buffer index offset 10-bit field */
205 /* Bit mask to access Inter-Frame Spacing field */
212 /* Delayed Send or Receive Time (40-bit) */
233 /* Suppress Auto-FCS Transmission (on this frame) */
239 /* Cancel Suppression of auto-FCS transmission (on the current frame) */
241 /* Transceiver Off. Force Transciever OFF abort TX or RX immediately */
253 * Host side receiver buffer pointer toggle - toggles 0/1
298 /* Mask receiver Reed Solomon Frame Sync Loss event */
339 /* External Sync Clock Reset */
370 /* Receiver Reed Solomon Frame Sync Loss */
402 /* Receiver Reed-Solomon Correction Status */
419 /* All TX events mask. */
466 /* Receive Non-Standard Preamble Length */
564 /* RX time tracking offset. This RXTOFS value is a 19-bit signed quantity */
566 /* This 8-bit field reports an internal re-sampler delay value */
569 * This 7-bit field reports the receive carrier phase adjustment
594 /* 40-bits = 5 bytes */
602 /* 16-bit Delay from Transmit to Antenna */
611 /* 7:0 TX _STATE Bits 3:0 */
653 * response (19:0 - unit 1us) timer
661 /* Wait-for-Response turn-around Time 20 bit field */
665 /* Auto-Acknowledgement turn-around Time */
672 /* Sniff Mode Configuration */
677 /* SNIFF Mode ON time. Specified in units of PAC */
681 * SNIFF Mode OFF time specified in units of approximately 1mkS,
687 /* TX Power Control */
742 /* Bits 0..3 TX channel number 0-15 selection */
745 /* Bits 4..7 RX channel number 0-15 selection */
770 /* Bits 22..26 TX Preamble Code selection, 1 to 24. */
776 /* Bit 17 This bit enables a non-standard DecaWave proprietary SFD sequence. */
779 /* Bit 20 Non-standard SFD in the transmitter */
782 /* Bit 21 Non-standard SFD in the receiver */
788 /* User-specified short/long TX/RX SFD sequences */
791 /* Decawave non-standard SFD length for 110 kbps */
793 /* Decawave non-standard SFD length for 850 kbps */
795 /* Decawave non-standard SFD length for 6.8 Mbps */
817 /* It is a 16-bit tuning register for the AGC. */
841 /* This 5-bit gain value relates to input noise power measurement. */
843 /* This 9-bit value relates to the input noise power measurement. */
852 * Sub-register 0x00 is the External clock synchronisation counter
856 /* External transmit synchronisation mode enable */
858 /* External receive synchronisation mode enable */
862 /* External timebase reset mode enable */
876 * Sub-register 0x08 is the External clock offset to first path 1 GHz counter,
890 /* Peripheral register bus 1 access - GPIO control */
894 /* Sub-register 0x00 is the GPIO Mode Control Register */
899 /* Mode Selection for GPIO0/RXOKLED */
901 /* Mode Selection for GPIO1/SFDLED */
903 /* Mode Selection for GPIO2/RXLED */
905 /* Mode Selection for GPIO3/TXLED */
907 /* Mode Selection for GPIO4/EXTPA */
909 /* Mode Selection for GPIO5/EXTTXE */
911 /* Mode Selection for GPIO6/EXTRXE */
913 /* Mode Selection for SYNC/GPIO7 */
915 /* Mode Selection for IRQ/GPIO8 */
929 /* Sub-register 0x08 is the GPIO Direction Control Register */
1016 /* Sub-register 0x0C is the GPIO data output register. */
1021 /* Sub-register 0x10 is the GPIO interrupt enable register */
1054 /* Sub-register 0x14 is the GPIO interrupt sense selection register */
1059 * Value 0 = High or Rising-Edge,
1060 * 1 = Low or falling-edge.
1072 /* Sub-register 0x18 is the GPIO interrupt mode selection register */
1076 /* GPIO IRQ Mode selection for GPIO0 input.
1090 /* Sub-register 0x1C is the GPIO interrupt "Both Edge" selection register */
1108 /* Sub-register 0x20 is the GPIO interrupt clear register */
1126 /* Sub-register 0x24 is the GPIO interrupt de-bounce enable register */
1130 /* GPIO IRQ de-bounce enable for GPIO0.
1131 * Value 1 = de-bounce enabled.
1132 * Value 0 = de-bounce disabled
1142 /* Value 1 = de-bounce enabled, 0 = de-bounce disabled */
1145 /* Sub-register 0x28 allows the raw state of the GPIO pin to be read. */
1163 /* Sub-register 0x02 is a 16-bit tuning register. */
1166 /* 7.2.40.2 Sub-Register 0x27:02 DRX_TUNE0b */
1175 /* 7.2.40.3 Sub-Register 0x27:04 DRX_TUNE1a */
1182 /* 7.2.40.4 Sub-Register 0x27:06 DRX_TUNE1b */
1190 /* 7.2.40.5 Sub-Register 0x27:08 DRX_TUNE2 */
1207 /* 7.2.40.7 Sub-Register 0x27:20 DRX_SFDTOC */
1212 /* 7.2.40.9 Sub-Register 0x27:24 DRX_PRETOC */
1217 /* 7.2.40.10 Sub-Register 0x27:26 DRX_TUNE4H */
1225 * Offset from DRX_CONF_ID in bytes to 21-bit signed
1232 /* 7.2.40.11 Sub-Register 0x27:2C - RXPACC_NOSAT */
1240 /* TX enable */
1248 /* Enable TX blocks */
1263 /* Analog TX Control Register */
1268 /* Transmit mixer Q-factor tuning register */
1270 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
1272 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
1274 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
1276 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
1278 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
1280 /* 32-bit value to program to Sub-Register 0x28:0C RF_TXCTRL */
1321 /* Continuous Wave (CW) Test Mode */
1389 /* Always-On register set */
1395 * low-power SLEEP or DEEPSLEEPstates.
1401 /* On Wake-up Run the (temperature and voltage) Analog-to-Digital Converters */
1403 /* On Wake-up turn on the Receiver */
1406 * On Wake-up load the EUI from OTP memory into Register file:
1411 * On Wake-up load configurations from the AON memory
1415 /* On Wake-up load the Length64 receiver operating parameter set */
1422 /* On Wake-up load the LDE microcode. */
1424 /* On Wake-up load the LDO tune value. */
1456 /* Address of low-power oscillator calibration value (lower byte) */
1458 /* Address of low-power oscillator calibration value (lower byte) */
1461 /* 32-bit configuration register for the always on block. */
1504 /* 32-bit register. The data value to be programmed into an OTP location */
1507 /* 16-bit register used to select the address within the OTP memory block */
1511 * This 11-bit field specifies the address within OTP memory
1519 /* This bit forces the OTP into manual read mode */
1540 /* 32-bit register. The data value read from an OTP location will appear here */
1544 * 32-bit register. The data value stored in the OTP SR (0x400) location
1550 * 8-bit special function register used to select and
1574 * 16-bit status register reporting the threshold that was used
1579 /*8-bit configuration register */
1598 /* 16-bit configuration register for setting the receive antenna delay */
1601 /* 16-bit LDE configuration tuning register */
1605 * 16-bit configuration register for setting
1655 /* Reed Solomon decoder (Frame Sync Loss) Error Event Counter */
1661 * The EVC_FCG field is a 12-bit counter of the frames received with
1668 * The EVC_FCE field is a 12-bit counter of the frames received with
1676 * The EVC_FFR field is a 12-bit counter of the frames rejected
1682 /* The EVC_OVR field is a 12-bit counter of receive overrun events */
1687 /* The EVC_STO field is a 12-bit counter of SFD Timeout Error events */
1691 /* The EVC_PTO field is a 12-bit counter of Preamble detection Timeout events */
1697 * The EVC_FWTO field is a 12-bit counter of receive
1704 * The EVC_TXFS field is a 12-bit counter of transmit frames sent.
1711 /* The EVC_HPW field is a 12-bit counter of Half Period Warnings. */
1715 /* The EVC_TPW field is a 12-bit counter of Transmitter Power-Up Warnings. */
1731 * This test mode is provided to help support regulatory approvals
1768 /* The TX clock will be disabled until it is required for a TX operation */
1770 /* Force TX clock enable and sourced clock from the 19.2 MHz XTI clock */
1772 /* Force TX clock enable and sourced from the 125 MHz PLL clock */
1774 /* Force TX clock off */
1782 /* GPIO De-bounce Clock Enable */
1786 /* Enable PLL2 on/off sequencing by SNIFF mode */
1799 /* Automatic transition from receive mode into the INIT state */
1803 * into SLEEP or DEEPSLEEP mode after transmission of a frame
1808 * into SLEEP mode after a receive attempt
1815 /* This enables a special 1 GHz clock used for some external SYNC modes */
1822 * Writing this to PMSC CONTROL 1 register (bits 10-3) disables
1827 * Writing this to PMSC CONTROL 1 register (bits 10-3) enables
1844 /* 32-bit LED control register. */
1878 /* Defaults from Table 38: Sub-Register 0x28:0C– RF_TXCTRL values */
1888 /* Defaults from Table 43: Sub-Register 0x2B:07 – FS_PLLCFG values */
1898 /* Defaults from Table 44: Sub-Register 0x2B:0B – FS_PLLTUNE values */
1908 /* Defaults from Table 37: Sub-Register 0x28:0B– RF_RXCTRLH values */
1918 /* Defaults from Table 40: Sub-Register 0x2A:0B – TC_PGDELAY */
1990 /* Defaults from Table 24: Sub-Register 0x23:04 – AGC_TUNE1 values */
2003 /* Decawave non-standard SFD lengths */
2010 /* Defaults from Table 30: Sub-Register 0x27:02 – DRX_TUNE0b values */
2026 /* Defaults from Table 31: Sub-Register 0x27:04 – DRX_TUNE1a values */
2040 /* Defaults from Table 33: Sub-Register 0x27:08 – DRX_TUNE2 values */
2058 * Sub-Register 0x2E:2804 – LDE_REPC configurations for (850 kbps & 6.8 Mbps)
2103 * constants for TX_FCTRL - Transmit Frame Control register.
2123 /* From Table 50: Sub-Register 0x2E:1806– LDE_CFG2 values */