297 static inline void dwt_reg_write_u32(const struct device *dev,  in dwt_reg_write_u32()  function
352 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, DWT_SYS_STATUS_OFFSET,  in dwt_disable_txrx()
377 	dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);  in dwt_enable_rx()
391 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,  in dwt_irq_handle_rx_cca()
512 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, flags_to_clear);  in dwt_irq_handle_rx()
529 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,  in dwt_irq_handle_tx()
541 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0,  in dwt_irq_handle_rxto()
561 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_ALL_RX_ERR);  in dwt_irq_handle_error()
813 		dwt_reg_write_u32(dev, DWT_DX_TIME_ID, 1, tx_time);  in dwt_tx()
843 	dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);  in dwt_tx()
1050 	dwt_reg_write_u32(dev, DWT_PMSC_ID, DWT_PMSC_CTRL0_OFFSET, pmsc_ctrl0);  in dwt_set_rx_mode()
1172 	dwt_reg_write_u32(dev, DWT_SYS_STATUS_ID, 0, DWT_SYS_STATUS_MASK_32);  in dwt_initialise_dev()
1379 	dwt_reg_write_u32(dev, DWT_SYS_CFG_ID, 0, sys_cfg);  in dwt_configure_rf_phy()
1399 	dwt_reg_write_u32(dev, DWT_FS_CTRL_ID, DWT_FS_PLLCFG_OFFSET, pll_cfg);  in dwt_configure_rf_phy()
1407 	dwt_reg_write_u32(dev, DWT_RF_CONF_ID, DWT_RF_TXCTRL_OFFSET, txctrl);  in dwt_configure_rf_phy()
1417 	dwt_reg_write_u32(dev, DWT_DRX_CONF_ID, DWT_DRX_TUNE2_OFFSET, tune2);  in dwt_configure_rf_phy()
1428 	dwt_reg_write_u32(dev, DWT_AGC_CTRL_ID, DWT_AGC_TUNE2_OFFSET,  in dwt_configure_rf_phy()
1461 	dwt_reg_write_u32(dev, DWT_CHAN_CTRL_ID, 0, chan_ctrl);  in dwt_configure_rf_phy()
1469 	dwt_reg_write_u32(dev, DWT_TX_FCTRL_ID, 0, tx_fctrl);  in dwt_configure_rf_phy()
1476 	dwt_reg_write_u32(dev, DWT_TX_POWER_ID, 0, power);  in dwt_configure_rf_phy()
1607 	dwt_reg_write_u32(dev, DWT_SYS_MASK_ID, 0,  in dw1000_init()