Lines Matching +full:clear +full:- +full:command +full:- +full:delay +full:- +full:us
4 * SPDX-License-Identifier: Apache-2.0
79 uint8_t rx_ns_sfd; /* non-standard SFD */
81 * (tx_shr_nsync + 1 + SFD_length - rx_pac_l)
136 .rx_sfd_to = (129 + 8 - 8),
158 struct dwt_context *ctx = dev->data; in dwt_spi_read()
159 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_spi_read()
187 if (spi_transceive(hi_cfg->bus.bus, ctx->spi_cfg, &tx, &rx)) { in dwt_spi_read()
189 return -EIO; in dwt_spi_read()
202 struct dwt_context *ctx = dev->data; in dwt_spi_write()
203 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_spi_write()
215 if (spi_write(hi_cfg->bus.bus, ctx->spi_cfg, &buf_set)) { in dwt_spi_write()
217 return -EIO; in dwt_spi_write()
324 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_setup_int()
330 gpio_pin_interrupt_configure_dt(&hi_cfg->irq_gpio, flags); in dwt_setup_int()
336 * Apply a receiver-only soft reset, in dwt_reset_rfrx()
385 struct dwt_context *ctx = dev->data; in dwt_irq_handle_rx_cca()
387 k_sem_give(&ctx->phy_sem); in dwt_irq_handle_rx_cca()
388 ctx->cca_busy = true; in dwt_irq_handle_rx_cca()
390 /* Clear all RX event bits */ in dwt_irq_handle_rx_cca()
397 struct dwt_context *ctx = dev->data; in dwt_irq_handle_rx()
420 pkt_len -= DWT_FCS_LENGTH; in dwt_irq_handle_rx()
423 pkt = net_pkt_rx_alloc_with_buffer(ctx->iface, pkt_len, in dwt_irq_handle_rx()
430 dwt_register_read(dev, DWT_RX_BUFFER_ID, 0, pkt_len, pkt->buffer->data); in dwt_irq_handle_rx()
433 net_buf_add(pkt->buffer, pkt_len); in dwt_irq_handle_rx()
434 fctrl = pkt->buffer->data; in dwt_irq_handle_rx()
442 /* Tracking offset value is a 19-bit signed integer */ in dwt_irq_handle_rx()
464 if (ctx->rf_cfg.prf == DWT_PRF_16M) { in dwt_irq_handle_rx()
474 (rx_pacc * rx_pacc)) - a_const; in dwt_irq_handle_rx()
491 if (ieee802154_handle_ack(ctx->iface, pkt) == NET_OK) { in dwt_irq_handle_rx()
498 LOG_HEXDUMP_DBG(pkt->buffer->data, pkt_len, "RX buffer:"); in dwt_irq_handle_rx()
500 if (net_recv_data(ctx->iface, pkt) == NET_OK) { in dwt_irq_handle_rx()
514 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) { in dwt_irq_handle_rx()
516 * Re-enable reception but in contrast to dwt_enable_rx() in dwt_irq_handle_rx()
526 struct dwt_context *ctx = dev->data; in dwt_irq_handle_tx()
528 /* Clear TX event bits */ in dwt_irq_handle_tx()
533 k_sem_give(&ctx->phy_sem); in dwt_irq_handle_tx()
538 struct dwt_context *ctx = dev->data; in dwt_irq_handle_rxto()
540 /* Clear RX timeout event bits */ in dwt_irq_handle_rxto()
550 if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) { in dwt_irq_handle_rxto()
551 k_sem_give(&ctx->phy_sem); in dwt_irq_handle_rxto()
552 ctx->cca_busy = false; in dwt_irq_handle_rxto()
558 struct dwt_context *ctx = dev->data; in dwt_irq_handle_error()
560 /* Clear RX error event bits */ in dwt_irq_handle_error()
568 if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) { in dwt_irq_handle_error()
569 k_sem_give(&ctx->phy_sem); in dwt_irq_handle_error()
570 ctx->cca_busy = true; in dwt_irq_handle_error()
574 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) { in dwt_irq_handle_error()
583 const struct device *dev = ctx->dev; in dwt_irq_work_handler()
586 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_irq_work_handler()
591 if (atomic_test_bit(&ctx->state, DWT_STATE_CCA)) { in dwt_irq_work_handler()
610 k_sem_give(&ctx->dev_lock); in dwt_irq_work_handler()
619 k_work_submit_to_queue(&dwt_work_queue, &ctx->irq_cb_work); in dwt_gpio_callback()
624 /* TODO: Implement HW-supported AUTOACK + frame pending bit handling. */ in dwt_get_capabilities()
631 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg; in dwt_get_pkt_duration_ns()
632 float t_psdu = rf_cfg->t_dsym * psdu_len * 8; in dwt_get_pkt_duration_ns()
634 return (rf_cfg->t_shr + rf_cfg->t_phr + t_psdu); in dwt_get_pkt_duration_ns()
639 struct dwt_context *ctx = dev->data; in dwt_cca()
644 if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_CCA)) { in dwt_cca()
646 return -EBUSY; in dwt_cca()
650 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_cca()
652 LOG_DBG("CCA duration %u us", cca_dur); in dwt_cca()
655 k_sem_give(&ctx->dev_lock); in dwt_cca()
657 k_sem_take(&ctx->phy_sem, K_FOREVER); in dwt_cca()
660 atomic_clear_bit(&ctx->state, DWT_STATE_CCA); in dwt_cca()
661 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) { in dwt_cca()
662 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_cca()
664 k_sem_give(&ctx->dev_lock); in dwt_cca()
667 return ctx->cca_busy ? -EBUSY : 0; in dwt_cca()
673 /* TODO: see description Sub-Register 0x23:02 – AGC_CTRL1 */ in dwt_ed()
675 return -ENOTSUP; in dwt_ed()
680 struct dwt_context *ctx = dev->data; in dwt_set_channel()
681 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg; in dwt_set_channel()
684 return -EINVAL; in dwt_set_channel()
688 return -ENOTSUP; in dwt_set_channel()
691 rf_cfg->channel = channel; in dwt_set_channel()
694 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_set_channel()
699 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) { in dwt_set_channel()
703 k_sem_give(&ctx->dev_lock); in dwt_set_channel()
710 struct dwt_context *ctx = dev->data; in dwt_set_pan_id()
712 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_set_pan_id()
714 k_sem_give(&ctx->dev_lock); in dwt_set_pan_id()
723 struct dwt_context *ctx = dev->data; in dwt_set_short_addr()
725 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_set_short_addr()
728 k_sem_give(&ctx->dev_lock); in dwt_set_short_addr()
738 struct dwt_context *ctx = dev->data; in dwt_set_ieee_addr()
744 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_set_ieee_addr()
747 k_sem_give(&ctx->dev_lock); in dwt_set_ieee_addr()
758 return -ENOTSUP; in dwt_filter()
762 return dwt_set_ieee_addr(dev, filter->ieee_addr); in dwt_filter()
764 return dwt_set_short_addr(dev, filter->short_addr); in dwt_filter()
766 return dwt_set_pan_id(dev, filter->pan_id); in dwt_filter()
769 return -ENOTSUP; in dwt_filter()
774 struct dwt_context *ctx = dev->data; in dwt_set_power()
784 struct dwt_context *ctx = dev->data; in dwt_tx()
785 size_t len = frag->len; in dwt_tx()
791 if (atomic_test_and_set_bit(&ctx->state, DWT_STATE_TX)) { in dwt_tx()
793 return -EBUSY; in dwt_tx()
796 k_sem_reset(&ctx->phy_sem); in dwt_tx()
797 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_tx()
804 * tx_time is the high 32-bit of the 40-bit system in dwt_tx()
812 /* DX_TIME is 40-bit register */ in dwt_tx()
824 LOG_HEXDUMP_DBG(frag->data, len, "TX buffer:"); in dwt_tx()
830 if (dwt_register_write(dev, DWT_TX_BUFFER_ID, 0, len, frag->data)) { in dwt_tx()
836 /* Clear TX buffer index offset, frame length, and length extension */ in dwt_tx()
854 LOG_WRN("Half Period Delay Warning"); in dwt_tx()
858 k_sem_give(&ctx->dev_lock); in dwt_tx()
860 k_sem_take(&ctx->phy_sem, K_FOREVER); in dwt_tx()
865 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_tx()
873 k_sem_give(&ctx->dev_lock); in dwt_tx()
879 atomic_clear_bit(&ctx->state, DWT_STATE_TX); in dwt_tx()
881 if (atomic_test_bit(&ctx->state, DWT_STATE_RX_DEF_ON)) { in dwt_tx()
882 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_tx()
884 k_sem_give(&ctx->dev_lock); in dwt_tx()
890 atomic_clear_bit(&ctx->state, DWT_STATE_TX); in dwt_tx()
891 k_sem_give(&ctx->dev_lock); in dwt_tx()
893 return -EIO; in dwt_tx()
910 struct dwt_context *ctx = dev->data; in dwt_configure()
936 return -EINVAL; in dwt_configure()
939 return -ENOTSUP; in dwt_configure()
942 /* driver-allocated attribute memory - constant across all driver instances */
968 struct dwt_context *ctx = dev->data; in dwt_attr_get()
969 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg; in dwt_attr_get()
971 value->phy_hrp_uwb_supported_nominal_prfs = in dwt_attr_get()
972 rf_cfg->prf == DWT_PRF_64M ? IEEE802154_PHY_HRP_UWB_NOMINAL_64_M in dwt_attr_get()
978 return -ENOENT; in dwt_attr_get()
987 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_hw_reset()
989 if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_OUTPUT_ACTIVE)) { in dwt_hw_reset()
990 LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin); in dwt_hw_reset()
991 return -EINVAL; in dwt_hw_reset()
995 gpio_pin_set_dt(&hi_cfg->rst_gpio, 0); in dwt_hw_reset()
998 if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) { in dwt_hw_reset()
999 LOG_ERR("Failed to configure GPIO pin %u", hi_cfg->rst_gpio.pin); in dwt_hw_reset()
1000 return -EINVAL; in dwt_hw_reset()
1007 * SPI speed in INIT state or for wake-up sequence,
1012 struct dwt_context *ctx = dev->data; in dwt_set_spi_slow()
1014 ctx->spi_cfg_slow.frequency = freq; in dwt_set_spi_slow()
1015 ctx->spi_cfg = &ctx->spi_cfg_slow; in dwt_set_spi_slow()
1021 const struct dwt_hi_cfg *hi_cfg = dev->config; in dwt_set_spi_fast()
1022 struct dwt_context *ctx = dev->data; in dwt_set_spi_fast()
1024 ctx->spi_cfg = &hi_cfg->bus.config; in dwt_set_spi_fast()
1029 struct dwt_context *ctx = dev->data; in dwt_set_rx_mode()
1030 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg; in dwt_set_rx_mode()
1041 t_on_us = (rx_sniff[0] + 1) * (BIT(3) << rf_cfg->rx_pac_l); in dwt_set_rx_mode()
1055 struct dwt_context *ctx = dev->data; in dwt_start()
1058 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_start()
1071 LOG_ERR("Failed to wake-up %p", dev); in dwt_start()
1072 k_sem_give(&ctx->dev_lock); in dwt_start()
1073 return -1; in dwt_start()
1091 /* Re-enable RX after packet reception */ in dwt_start()
1092 atomic_set_bit(&ctx->state, DWT_STATE_RX_DEF_ON); in dwt_start()
1094 k_sem_give(&ctx->dev_lock); in dwt_start()
1103 struct dwt_context *ctx = dev->data; in dwt_stop()
1105 k_sem_take(&ctx->dev_lock, K_FOREVER); in dwt_stop()
1113 k_sem_give(&ctx->dev_lock); in dwt_stop()
1160 struct dwt_context *ctx = dev->data; in dwt_initialise_dev()
1165 ctx->sleep_mode = 0; in dwt_initialise_dev()
1171 /* Clear all status flags */ in dwt_initialise_dev()
1198 ctx->sleep_mode |= DWT_AON_WCFG_ONW_LLDO; in dwt_initialise_dev()
1227 ctx->sleep_mode |= DWT_AON_WCFG_ONW_LLDE; in dwt_initialise_dev()
1234 return -EIO; in dwt_initialise_dev()
1239 /* Setup antenna delay values */ in dwt_initialise_dev()
1245 /* Clear AON_CFG1 register */ in dwt_initialise_dev()
1249 * - On wake-up load configurations from the AON memory in dwt_initialise_dev()
1250 * - preserve sleep mode configuration in dwt_initialise_dev()
1251 * - On Wake-up load the LDE microcode in dwt_initialise_dev()
1252 * - When available, on wake-up load the LDO tune value in dwt_initialise_dev()
1254 ctx->sleep_mode |= DWT_AON_WCFG_ONW_LDC | in dwt_initialise_dev()
1257 ctx->sleep_mode); in dwt_initialise_dev()
1258 LOG_DBG("sleep mode 0x%04x", ctx->sleep_mode); in dwt_initialise_dev()
1272 struct dwt_context *ctx = dev->data; in dwt_configure_rf_phy()
1273 struct dwt_phy_config *rf_cfg = &ctx->rf_cfg; in dwt_configure_rf_phy()
1274 uint8_t chan = rf_cfg->channel; in dwt_configure_rf_phy()
1275 uint8_t prf_idx = rf_cfg->prf; in dwt_configure_rf_phy()
1296 return -ENOTSUP; in dwt_configure_rf_phy()
1299 if (rf_cfg->rx_shr_code >= ARRAY_SIZE(dwt_lde_repc_defs)) { in dwt_configure_rf_phy()
1301 rf_cfg->rx_shr_code); in dwt_configure_rf_phy()
1302 return -ENOTSUP; in dwt_configure_rf_phy()
1307 return -ENOTSUP; in dwt_configure_rf_phy()
1310 if (rf_cfg->rx_pac_l >= DWT_NUMOF_PACS) { in dwt_configure_rf_phy()
1311 LOG_ERR("RX PAC not supported %u", rf_cfg->rx_pac_l); in dwt_configure_rf_phy()
1312 return -ENOTSUP; in dwt_configure_rf_phy()
1315 if (rf_cfg->rx_ns_sfd > 1) { in dwt_configure_rf_phy()
1317 return -ENOTSUP; in dwt_configure_rf_phy()
1320 if (rf_cfg->tx_shr_nsync >= DWT_NUM_OF_PLEN) { in dwt_configure_rf_phy()
1322 return -ENOTSUP; in dwt_configure_rf_phy()
1325 lde_repc = dwt_lde_repc_defs[rf_cfg->rx_shr_code]; in dwt_configure_rf_phy()
1327 sfdto = rf_cfg->rx_sfd_to; in dwt_configure_rf_phy()
1332 tune2 = dwt_tune2_defs[prf_idx][rf_cfg->rx_pac_l]; in dwt_configure_rf_phy()
1334 tune0b = dwt_tune0b_defs[rf_cfg->dr][rf_cfg->rx_ns_sfd]; in dwt_configure_rf_phy()
1340 /* Don't allow 0 - SFD timeout will always be enabled */ in dwt_configure_rf_phy()
1348 if (rf_cfg->dr == DWT_BR_110K) { in dwt_configure_rf_phy()
1356 if (rf_cfg->tx_shr_nsync == DWT_PLEN_64) { in dwt_configure_rf_phy()
1366 if (rf_cfg->prf == DWT_PRF_64M) { in dwt_configure_rf_phy()
1372 if (rf_cfg->prf == DWT_PRF_64M) { in dwt_configure_rf_phy()
1388 if (rf_cfg->prf == DWT_PRF_64M) { in dwt_configure_rf_phy()
1431 if (rf_cfg->rx_ns_sfd) { in dwt_configure_rf_phy()
1438 dwt_ns_sfdlen[rf_cfg->dr]); in dwt_configure_rf_phy()
1439 LOG_DBG("USR_SFDLEN: 0x%02x", dwt_ns_sfdlen[rf_cfg->dr]); in dwt_configure_rf_phy()
1449 chan_ctrl |= (BIT(rf_cfg->prf) << DWT_CHAN_CTRL_RXFPRF_SHIFT) & in dwt_configure_rf_phy()
1453 chan_ctrl |= (rf_cfg->tx_shr_code << DWT_CHAN_CTRL_TX_PCOD_SHIFT) & in dwt_configure_rf_phy()
1457 chan_ctrl |= (rf_cfg->rx_shr_code << DWT_CHAN_CTRL_RX_PCOD_SHIFT) & in dwt_configure_rf_phy()
1465 tx_fctrl = dwt_plen_cfg[rf_cfg->tx_shr_nsync] | in dwt_configure_rf_phy()
1466 (BIT(rf_cfg->prf) << DWT_TX_FCTRL_TXPRF_SHFT) | in dwt_configure_rf_phy()
1467 (rf_cfg->dr << DWT_TX_FCTRL_TXBR_SHFT); in dwt_configure_rf_phy()
1472 /* Set the Pulse Generator Delay */ in dwt_configure_rf_phy()
1489 * From (9.4) Std 802.15.4-2011 in dwt_configure_rf_phy()
1500 uint16_t nsync = BIT(rf_cfg->tx_shr_nsync + 6); in dwt_configure_rf_phy()
1502 if (rf_cfg->prf == DWT_PRF_64M) { in dwt_configure_rf_phy()
1503 rf_cfg->t_shr = UWB_PHY_TPSYM_PRF64 * in dwt_configure_rf_phy()
1506 rf_cfg->t_shr = UWB_PHY_TPSYM_PRF16 * in dwt_configure_rf_phy()
1510 if (rf_cfg->dr == DWT_BR_6M8) { in dwt_configure_rf_phy()
1511 rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_6M8; in dwt_configure_rf_phy()
1512 rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_6M8 / 0.44; in dwt_configure_rf_phy()
1513 } else if (rf_cfg->dr == DWT_BR_850K) { in dwt_configure_rf_phy()
1514 rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_850K; in dwt_configure_rf_phy()
1515 rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_850K / 0.44; in dwt_configure_rf_phy()
1517 rf_cfg->t_phr = UWB_PHY_NUMOF_SYM_PHR * UWB_PHY_TDSYM_PHR_110K; in dwt_configure_rf_phy()
1518 rf_cfg->t_dsym = UWB_PHY_TDSYM_DATA_110K / 0.44; in dwt_configure_rf_phy()
1526 struct dwt_context *ctx = dev->data; in dw1000_init()
1527 const struct dwt_hi_cfg *hi_cfg = dev->config; in dw1000_init()
1530 k_sem_init(&ctx->phy_sem, 0, 1); in dw1000_init()
1533 memcpy(&ctx->spi_cfg_slow, &hi_cfg->bus.config, sizeof(ctx->spi_cfg_slow)); in dw1000_init()
1534 ctx->spi_cfg_slow.frequency = DWT_SPI_SLOW_FREQ; in dw1000_init()
1536 if (!spi_is_ready_dt(&hi_cfg->bus)) { in dw1000_init()
1538 return -ENODEV; in dw1000_init()
1544 if (!gpio_is_ready_dt(&hi_cfg->irq_gpio)) { in dw1000_init()
1546 return -ENODEV; in dw1000_init()
1549 if (gpio_pin_configure_dt(&hi_cfg->irq_gpio, GPIO_INPUT)) { in dw1000_init()
1550 LOG_ERR("Unable to configure GPIO pin %u", hi_cfg->irq_gpio.pin); in dw1000_init()
1551 return -EINVAL; in dw1000_init()
1554 gpio_init_callback(&(ctx->gpio_cb), dwt_gpio_callback, in dw1000_init()
1555 BIT(hi_cfg->irq_gpio.pin)); in dw1000_init()
1557 if (gpio_add_callback(hi_cfg->irq_gpio.port, &(ctx->gpio_cb))) { in dw1000_init()
1559 return -EINVAL; in dw1000_init()
1563 if (!gpio_is_ready_dt(&hi_cfg->rst_gpio)) { in dw1000_init()
1565 return -ENODEV; in dw1000_init()
1568 if (gpio_pin_configure_dt(&hi_cfg->rst_gpio, GPIO_INPUT)) { in dw1000_init()
1569 LOG_ERR("Unable to configure GPIO pin %u", hi_cfg->rst_gpio.pin); in dw1000_init()
1570 return -EINVAL; in dw1000_init()
1579 return -ENODEV; in dw1000_init()
1584 return -EIO; in dw1000_init()
1589 return -EIO; in dw1000_init()
1592 /* Allow Beacon, Data, Acknowledgement, MAC command */ in dw1000_init()
1598 * - transmit frame sent, in dw1000_init()
1599 * - receiver FCS good, in dw1000_init()
1600 * - receiver PHY header error, in dw1000_init()
1601 * - receiver FCS error, in dw1000_init()
1602 * - receiver Reed Solomon Frame Sync Loss, in dw1000_init()
1603 * - receive Frame Wait Timeout, in dw1000_init()
1604 * - preamble detection timeout, in dw1000_init()
1605 * - receive SFD timeout in dw1000_init()
1618 ctx->dev = dev; in dw1000_init()
1624 k_work_init(&ctx->irq_cb_work, dwt_irq_work_handler); in dw1000_init()
1635 struct dwt_context *dw1000 = dev->data; in get_mac()
1637 sys_rand_get(dw1000->mac_addr, sizeof(dw1000->mac_addr)); in get_mac()
1639 dw1000->mac_addr[0] = (dw1000->mac_addr[0] & ~0x01) | 0x02; in get_mac()
1641 return dw1000->mac_addr; in get_mac()
1647 struct dwt_context *dw1000 = dev->data; in dwt_iface_api_init()
1652 dw1000->iface = iface; in dwt_iface_api_init()
1675 #define DWT_PSDU_LENGTH (127 - DWT_FCS_LENGTH)