Lines Matching +full:mixed +full:- +full:mode
4 * SPDX-License-Identifier: Apache-2.0
133 size_t ccc_target_idx; /* Current target index, used for filling C-FIFO */
163 * Determine I3C bus mode from the i2c devices on the bus.
166 * Mode.
174 enum i3c_bus_mode mode = I3C_BUS_MODE_PURE; in i3c_bus_mode() local
176 for (int i = 0; i < dev_list->num_i2c; i++) { in i3c_bus_mode()
177 switch (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr)) { in i3c_bus_mode()
179 if (mode < I3C_BUS_MODE_MIXED_FAST) { in i3c_bus_mode()
180 mode = I3C_BUS_MODE_MIXED_FAST; in i3c_bus_mode()
184 if (mode < I3C_BUS_MODE_MIXED_LIMITED) { in i3c_bus_mode()
185 mode = I3C_BUS_MODE_MIXED_LIMITED; in i3c_bus_mode()
189 if (mode < I3C_BUS_MODE_MIXED_SLOW) { in i3c_bus_mode()
190 mode = I3C_BUS_MODE_MIXED_SLOW; in i3c_bus_mode()
194 mode = I3C_BUS_MODE_INVALID; in i3c_bus_mode()
198 return mode; in i3c_bus_mode()
203 for (int i = 0; i < dev_list->num_i2c; i++) { in get_i3c_lvr_ic_mode()
204 if (I3C_LVR_I2C_DEV_IDX(dev_list->i2c[i].lvr) == I3C_LVR_I2C_DEV_IDX_0) { in get_i3c_lvr_ic_mode()
205 if (I3C_LVR_I2C_MODE(dev_list->i2c[i].lvr) == I3C_LVR_I2C_FM_MODE) { in get_i3c_lvr_ic_mode()
215 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_is_i3c()
216 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_is_i3c()
218 return (curr_msg->msg_type == LL_I3C_CONTROLLER_MTYPE_PRIVATE); in i3c_stm32_curr_msg_is_i3c()
223 struct i3c_stm32_data *data = dev->data; in i3c_stm32_arbitration_header_config()
224 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_arbitration_header_config()
225 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_arbitration_header_config()
226 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_arbitration_header_config()
229 if (curr_msg->i3c_msg_ctrl_ptr->flags & I3C_MSG_NBCH) { in i3c_stm32_arbitration_header_config()
242 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_init()
243 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_init()
250 curr_msg->target_addr = tgt_addr; in i3c_stm32_curr_msg_init()
251 curr_msg->xfer_offset = 0; in i3c_stm32_curr_msg_init()
252 curr_msg->num_msgs = num_msgs; in i3c_stm32_curr_msg_init()
253 curr_msg->ctrl_msg_idx = 0; in i3c_stm32_curr_msg_init()
254 curr_msg->status_msg_idx = 0; in i3c_stm32_curr_msg_init()
255 curr_msg->xfer_msg_idx = 0; in i3c_stm32_curr_msg_init()
259 curr_msg->msg_type = LL_I3C_CONTROLLER_MTYPE_PRIVATE; in i3c_stm32_curr_msg_init()
260 curr_msg->i3c_msg_ptr = i3c_msgs; in i3c_stm32_curr_msg_init()
261 curr_msg->i3c_msg_ctrl_ptr = i3c_msgs; in i3c_stm32_curr_msg_init()
262 curr_msg->i3c_msg_status_ptr = i3c_msgs; in i3c_stm32_curr_msg_init()
265 curr_msg->msg_type = LL_I3C_CONTROLLER_MTYPE_LEGACY_I2C; in i3c_stm32_curr_msg_init()
266 curr_msg->i2c_msg_ptr = i2c_msgs; in i3c_stm32_curr_msg_init()
267 curr_msg->i2c_msg_ctrl_ptr = i2c_msgs; in i3c_stm32_curr_msg_init()
276 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_control_get_dir()
277 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_control_get_dir()
280 return (((curr_msg->i3c_msg_ctrl_ptr->flags & I3C_MSG_RW_MASK) == I3C_MSG_READ) in i3c_stm32_curr_msg_control_get_dir()
285 return (((curr_msg->i2c_msg_ctrl_ptr->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) in i3c_stm32_curr_msg_control_get_dir()
292 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_control_get_len()
293 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_control_get_len()
295 return (i3c_stm32_curr_msg_is_i3c(dev)) ? curr_msg->i3c_msg_ctrl_ptr->len in i3c_stm32_curr_msg_control_get_len()
296 : curr_msg->i2c_msg_ctrl_ptr->len; in i3c_stm32_curr_msg_control_get_len()
301 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_control_get_end()
302 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_control_get_end()
304 return ((curr_msg->ctrl_msg_idx < (curr_msg->num_msgs - 1)) ? LL_I3C_GENERATE_RESTART in i3c_stm32_curr_msg_control_get_end()
310 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_control_next()
311 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_control_next()
313 if (curr_msg->ctrl_msg_idx >= curr_msg->num_msgs) { in i3c_stm32_curr_msg_control_next()
315 return -EFAULT; in i3c_stm32_curr_msg_control_next()
319 curr_msg->i3c_msg_ctrl_ptr++; in i3c_stm32_curr_msg_control_next()
321 curr_msg->i2c_msg_ctrl_ptr++; in i3c_stm32_curr_msg_control_next()
324 curr_msg->ctrl_msg_idx++; in i3c_stm32_curr_msg_control_next()
331 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_status_update_num_xfer()
332 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_status_update_num_xfer()
334 if (curr_msg->status_msg_idx >= curr_msg->num_msgs) { in i3c_stm32_curr_msg_status_update_num_xfer()
336 return -EFAULT; in i3c_stm32_curr_msg_status_update_num_xfer()
341 curr_msg->i3c_msg_status_ptr->num_xfer = num_xfer; in i3c_stm32_curr_msg_status_update_num_xfer()
349 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_status_next()
350 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_status_next()
352 if (curr_msg->status_msg_idx >= curr_msg->num_msgs) { in i3c_stm32_curr_msg_status_next()
354 return -EFAULT; in i3c_stm32_curr_msg_status_next()
358 curr_msg->i3c_msg_status_ptr++; in i3c_stm32_curr_msg_status_next()
359 curr_msg->status_msg_idx++; in i3c_stm32_curr_msg_status_next()
368 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_xfer_get_buf()
369 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_xfer_get_buf()
371 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) { in i3c_stm32_curr_msg_xfer_get_buf()
373 return -EFAULT; in i3c_stm32_curr_msg_xfer_get_buf()
377 *buf = curr_msg->i3c_msg_ptr->buf; in i3c_stm32_curr_msg_xfer_get_buf()
378 *len = curr_msg->i3c_msg_ptr->len; in i3c_stm32_curr_msg_xfer_get_buf()
380 *buf = curr_msg->i2c_msg_ptr->buf; in i3c_stm32_curr_msg_xfer_get_buf()
381 *len = curr_msg->i2c_msg_ptr->len; in i3c_stm32_curr_msg_xfer_get_buf()
384 *offset = &curr_msg->xfer_offset; in i3c_stm32_curr_msg_xfer_get_buf()
389 /* This method is only used in DMA mode */
393 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_xfer_is_read()
394 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_xfer_is_read()
396 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) { in i3c_stm32_curr_msg_xfer_is_read()
402 return ((curr_msg->i3c_msg_ptr->flags & I3C_MSG_RW_MASK) == I3C_MSG_READ); in i3c_stm32_curr_msg_xfer_is_read()
405 return ((curr_msg->i2c_msg_ptr->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ); in i3c_stm32_curr_msg_xfer_is_read()
411 struct i3c_stm32_data *data = dev->data; in i3c_stm32_curr_msg_xfer_next()
412 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_curr_msg_xfer_next()
414 if (curr_msg->xfer_msg_idx >= curr_msg->num_msgs) { in i3c_stm32_curr_msg_xfer_next()
416 return -EFAULT; in i3c_stm32_curr_msg_xfer_next()
420 curr_msg->i3c_msg_ptr++; in i3c_stm32_curr_msg_xfer_next()
422 curr_msg->i2c_msg_ptr++; in i3c_stm32_curr_msg_xfer_next()
425 curr_msg->xfer_msg_idx++; in i3c_stm32_curr_msg_xfer_next()
426 curr_msg->xfer_offset = 0; in i3c_stm32_curr_msg_xfer_next()
435 struct i3c_stm32_config *config = (struct i3c_stm32_config *)dev->config; in i3c_stm32_activate()
438 ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in i3c_stm32_activate()
443 if (clock_control_on(clk, (clock_control_subsys_t)&config->pclken[0]) != 0) { in i3c_stm32_activate()
444 return -EIO; in i3c_stm32_activate()
452 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_calc_scll_od_sclh_i2c()
458 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
460 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2; in i3c_stm32_calc_scll_od_sclh_i2c()
462 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FMP_NS * i3c_clock, 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
467 return -EINVAL; in i3c_stm32_calc_scll_od_sclh_i2c()
472 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
474 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - *scll_od - 2; in i3c_stm32_calc_scll_od_sclh_i2c()
478 DIV_ROUND_UP(STM32_I3C_SCLH_I2C_MIN_FM_NS * i3c_clock, 1000000000ull) - 1) { in i3c_stm32_calc_scll_od_sclh_i2c()
482 return -EINVAL; in i3c_stm32_calc_scll_od_sclh_i2c()
485 if (config->drv_cfg.dev_list.num_i2c > 0) { in i3c_stm32_calc_scll_od_sclh_i2c()
486 enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list); in i3c_stm32_calc_scll_od_sclh_i2c() local
488 if (mode == I3C_BUS_MODE_MIXED_FAST) { in i3c_stm32_calc_scll_od_sclh_i2c()
489 if (get_i3c_lvr_ic_mode(&config->drv_cfg.dev_list) == in i3c_stm32_calc_scll_od_sclh_i2c()
495 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
497 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - in i3c_stm32_calc_scll_od_sclh_i2c()
498 *scll_od - 2; in i3c_stm32_calc_scll_od_sclh_i2c()
504 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
506 *sclh_i2c = DIV_ROUND_UP(i3c_clock, i2c_bus_freq) - in i3c_stm32_calc_scll_od_sclh_i2c()
507 *scll_od - 2; in i3c_stm32_calc_scll_od_sclh_i2c()
510 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
515 return -EINVAL; in i3c_stm32_calc_scll_od_sclh_i2c()
521 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
526 return -EINVAL; in i3c_stm32_calc_scll_od_sclh_i2c()
529 return -EINVAL; in i3c_stm32_calc_scll_od_sclh_i2c()
534 1000000000ull) - in i3c_stm32_calc_scll_od_sclh_i2c()
547 *sclh_i3c = DIV_ROUND_UP(STM32_I3C_SCLH_I3C_MIN_NS * i3c_clock, 1000000000ull) - 1; in i3c_stm32_calc_scll_pp_sclh_i3c()
548 *scll_pp = DIV_ROUND_UP(i3c_clock, i3c_bus_freq) - *sclh_i3c - 2; in i3c_stm32_calc_scll_pp_sclh_i3c()
550 if (*scll_pp < DIV_ROUND_UP(STM32_I3C_SCLL_PP_MIN_NS * i3c_clock, 1000000000ull) - 1) { in i3c_stm32_calc_scll_pp_sclh_i3c()
553 return -EINVAL; in i3c_stm32_calc_scll_pp_sclh_i3c()
562 const struct i3c_stm32_config *cfg = dev->config; in i3c_stm32_config_clk_wave()
563 struct i3c_stm32_data *data = dev->data; in i3c_stm32_config_clk_wave()
565 I3C_TypeDef *i3c = cfg->i3c; in i3c_stm32_config_clk_wave()
567 uint32_t i2c_bus_freq = data->drv_data.ctrl_config.scl.i2c; in i3c_stm32_config_clk_wave()
568 uint32_t i3c_bus_freq = data->drv_data.ctrl_config.scl.i3c; in i3c_stm32_config_clk_wave()
570 if (clock_control_get_rate(clk, (clock_control_subsys_t)&cfg->pclken[0], &i3c_clock) < 0) { in i3c_stm32_config_clk_wave()
572 return -EIO; in i3c_stm32_config_clk_wave()
614 * @retval -EIO General Input/Output errors.
615 * @retval -ENOSYS If not implemented.
619 struct i3c_stm32_data *data = dev->data; in i3c_stm32_config_get()
622 return -EINVAL; in i3c_stm32_config_get()
625 (void)memcpy(config, &data->drv_data.ctrl_config, sizeof(data->drv_data.ctrl_config)); in i3c_stm32_config_get()
632 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_config_ctrl_bus_char()
633 struct i3c_stm32_data *data = dev->data; in i3c_stm32_config_ctrl_bus_char()
635 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_config_ctrl_bus_char()
637 uint32_t i2c_bus_freq = data->drv_data.ctrl_config.scl.i2c; in i3c_stm32_config_ctrl_bus_char()
642 if (clock_control_get_rate(clk, (clock_control_subsys_t)&config->pclken[0], &i3c_clock) < in i3c_stm32_config_ctrl_bus_char()
645 return -EIO; in i3c_stm32_config_ctrl_bus_char()
652 /* Mixed bus with I2C FM+ device */ in i3c_stm32_config_ctrl_bus_char()
654 (STM32_I3C_TBUF_FMP_MIN_NS * i3c_clock / 1e9 - 0.5) / 2); in i3c_stm32_config_ctrl_bus_char()
656 /* Mixed bus with I2C FM device */ in i3c_stm32_config_ctrl_bus_char()
658 (STM32_I3C_TBUF_FM_MIN_NS * i3c_clock / 1e9 - 0.5) / 2); in i3c_stm32_config_ctrl_bus_char()
661 if (config->drv_cfg.dev_list.num_i2c > 0) { in i3c_stm32_config_ctrl_bus_char()
662 enum i3c_bus_mode mode = i3c_bus_mode(&config->drv_cfg.dev_list); in i3c_stm32_config_ctrl_bus_char() local
664 if (mode == I3C_BUS_MODE_MIXED_FAST) { in i3c_stm32_config_ctrl_bus_char()
665 if (get_i3c_lvr_ic_mode(&config->drv_cfg.dev_list) == in i3c_stm32_config_ctrl_bus_char()
667 /* Mixed bus with I2C FM device */ in i3c_stm32_config_ctrl_bus_char()
669 (STM32_I3C_TBUF_FM_MIN_NS * i3c_clock / 1e9 - 0.5) / in i3c_stm32_config_ctrl_bus_char()
672 /* Mixed bus with I2C FM+ device */ in i3c_stm32_config_ctrl_bus_char()
674 (STM32_I3C_TBUF_FMP_MIN_NS * i3c_clock / 1e9 - in i3c_stm32_config_ctrl_bus_char()
679 return -EINVAL; in i3c_stm32_config_ctrl_bus_char()
684 (uint8_t)ceil((STM32_I3C_TCAS_MIN_NS * i3c_clock / 1e9 - 0.5) / 2); in i3c_stm32_config_ctrl_bus_char()
688 aval = DIV_ROUND_UP(1000ull * i3c_clock, 1000000000ull) - 1; in i3c_stm32_config_ctrl_bus_char()
699 /* Configures the I3C module in controller mode */
705 return -ENOTSUP; in i3c_stm32_configure()
708 struct i3c_stm32_data *data = dev->data; in i3c_stm32_configure()
711 if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) { in i3c_stm32_configure()
712 return -EINVAL; in i3c_stm32_configure()
715 data->drv_data.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c; in i3c_stm32_configure()
716 data->drv_data.ctrl_config.scl.i2c = ctrl_cfg->scl.i2c; in i3c_stm32_configure()
741 struct i3c_stm32_data *data = dev->data; in i3c_stm32_i2c_configure()
742 struct i3c_config_controller *ctrl_config = &data->drv_data.ctrl_config; in i3c_stm32_i2c_configure()
746 ctrl_config->scl.i2c = 400000; in i3c_stm32_i2c_configure()
749 ctrl_config->scl.i2c = 1000000; in i3c_stm32_i2c_configure()
752 return -EINVAL; in i3c_stm32_i2c_configure()
772 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_device_find()
774 return i3c_dev_list_find(&config->drv_cfg.dev_list, id); in i3c_stm32_device_find()
781 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_end_dma_requests()
782 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_end_dma_requests()
797 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_prepare_dma_requests()
798 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_prepare_dma_requests()
815 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_flush_all_fifo()
816 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_flush_all_fifo()
826 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_log_err_type()
827 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_log_err_type()
865 struct i3c_stm32_data *data = dev->data; in i3c_stm32_clear_err()
866 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_clear_err()
867 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_clear_err()
871 /* Re-enable arbirtation header after exiting from error caused by legacy I2C msg */ in i3c_stm32_clear_err()
879 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo); in i3c_stm32_clear_err()
880 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo); in i3c_stm32_clear_err()
883 data->msg_state = STM32_I3C_MSG_IDLE; in i3c_stm32_clear_err()
884 data->sf_state = STM32_I3C_SF_IDLE; in i3c_stm32_clear_err()
886 k_mutex_unlock(&data->bus_mutex); in i3c_stm32_clear_err()
902 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_fill_tx_fifo()
903 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_fill_tx_fifo()
940 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_drain_rx_fifo()
941 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_drain_rx_fifo()
968 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_do_ccc()
969 struct i3c_stm32_data *data = dev->data; in i3c_stm32_do_ccc()
970 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_do_ccc()
975 if (payload->ccc.id == I3C_CCC_ENTDAA) { in i3c_stm32_do_ccc()
976 return -EINVAL; in i3c_stm32_do_ccc()
981 (payload->targets.payloads == NULL || payload->targets.num_targets == 0)) { in i3c_stm32_do_ccc()
982 return -EINVAL; in i3c_stm32_do_ccc()
985 if (payload->ccc.data_len > 0 && payload->ccc.data == NULL) { in i3c_stm32_do_ccc()
986 return -EINVAL; in i3c_stm32_do_ccc()
989 k_mutex_lock(&data->bus_mutex, K_FOREVER); in i3c_stm32_do_ccc()
1003 data->msg_state = STM32_I3C_MSG_CCC; in i3c_stm32_do_ccc()
1004 data->ccc_payload = payload; in i3c_stm32_do_ccc()
1005 data->ccc_target_idx = 0; in i3c_stm32_do_ccc()
1006 data->ccc_target_payload = payload->targets.payloads; in i3c_stm32_do_ccc()
1008 payload->ccc.num_xfer = 0; in i3c_stm32_do_ccc()
1010 for (size_t i = 0; i < payload->targets.num_targets; i++) { in i3c_stm32_do_ccc()
1011 payload->targets.payloads[i].num_xfer = 0; in i3c_stm32_do_ccc()
1015 LL_I3C_ControllerHandleCCC(i3c, payload->ccc.id, payload->ccc.data_len, in i3c_stm32_do_ccc()
1021 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) { in i3c_stm32_do_ccc()
1025 return -ETIMEDOUT; in i3c_stm32_do_ccc()
1028 if (data->msg_state == STM32_I3C_MSG_ERR) { in i3c_stm32_do_ccc()
1032 return -EIO; in i3c_stm32_do_ccc()
1037 k_mutex_unlock(&data->bus_mutex); in i3c_stm32_do_ccc()
1045 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_do_daa()
1046 struct i3c_stm32_data *data = dev->data; in i3c_stm32_do_daa()
1047 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_do_daa()
1049 k_mutex_lock(&data->bus_mutex, K_FOREVER); in i3c_stm32_do_daa()
1057 data->msg_state = STM32_I3C_MSG_DAA; in i3c_stm32_do_daa()
1068 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) { in i3c_stm32_do_daa()
1069 return -ETIMEDOUT; in i3c_stm32_do_daa()
1072 if (data->msg_state == STM32_I3C_MSG_ERR) { in i3c_stm32_do_daa()
1077 return -EIO; in i3c_stm32_do_daa()
1080 k_mutex_unlock(&data->bus_mutex); in i3c_stm32_do_daa()
1089 struct i3c_stm32_data *data = dev->data; in i3c_stm32_dma_msg_control_fifo_config()
1092 data->dma_tc.blk_cfg.source_address = (uint32_t)data->control_fifo; in i3c_stm32_dma_msg_control_fifo_config()
1093 data->dma_tc.blk_cfg.block_size = data->fifo_len; in i3c_stm32_dma_msg_control_fifo_config()
1095 ret = dma_config(data->dma_tc.dma_dev, data->dma_tc.dma_channel, &data->dma_tc.dma_cfg); in i3c_stm32_dma_msg_control_fifo_config()
1099 return -EINVAL; in i3c_stm32_dma_msg_control_fifo_config()
1102 if (dma_start(data->dma_tc.dma_dev, data->dma_tc.dma_channel)) { in i3c_stm32_dma_msg_control_fifo_config()
1104 return -EFAULT; in i3c_stm32_dma_msg_control_fifo_config()
1112 struct i3c_stm32_data *data = dev->data; in i3c_stm32_dma_msg_status_fifo_config()
1115 data->dma_rs.blk_cfg.dest_address = (uint32_t)data->status_fifo; in i3c_stm32_dma_msg_status_fifo_config()
1116 data->dma_rs.blk_cfg.block_size = data->fifo_len; in i3c_stm32_dma_msg_status_fifo_config()
1118 ret = dma_config(data->dma_rs.dma_dev, data->dma_rs.dma_channel, &data->dma_rs.dma_cfg); in i3c_stm32_dma_msg_status_fifo_config()
1122 return -EINVAL; in i3c_stm32_dma_msg_status_fifo_config()
1125 if (dma_start(data->dma_rs.dma_dev, data->dma_rs.dma_channel)) { in i3c_stm32_dma_msg_status_fifo_config()
1127 return -EFAULT; in i3c_stm32_dma_msg_status_fifo_config()
1136 struct i3c_stm32_data *data = dev->data; in i3c_stm32_dma_msg_config()
1140 dma_stream = &(data->dma_rx); in i3c_stm32_dma_msg_config()
1141 dma_stream->blk_cfg.dest_address = buf_addr; in i3c_stm32_dma_msg_config()
1143 dma_stream = &(data->dma_tx); in i3c_stm32_dma_msg_config()
1144 dma_stream->blk_cfg.source_address = buf_addr; in i3c_stm32_dma_msg_config()
1149 dma_stream->blk_cfg.block_size = buf_len; in i3c_stm32_dma_msg_config()
1150 ret = dma_config(dma_stream->dma_dev, dma_stream->dma_channel, &dma_stream->dma_cfg); in i3c_stm32_dma_msg_config()
1154 return -EINVAL; in i3c_stm32_dma_msg_config()
1157 if (dma_start(dma_stream->dma_dev, dma_stream->dma_channel)) { in i3c_stm32_dma_msg_config()
1159 return -EFAULT; in i3c_stm32_dma_msg_config()
1167 struct i3c_stm32_data *data = dev->data; in i3c_stm32_transfer_begin()
1168 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_transfer_begin()
1169 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_transfer_begin()
1171 data->msg_state = STM32_I3C_MSG; in i3c_stm32_transfer_begin()
1172 data->sf_state = STM32_I3C_SF; in i3c_stm32_transfer_begin()
1180 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_transfer_begin()
1182 data->fifo_len = curr_msg->num_msgs * sizeof(uint32_t); in i3c_stm32_transfer_begin()
1183 data->control_fifo = k_heap_alloc(&stm32_i3c_fifo_heap, data->fifo_len, K_FOREVER); in i3c_stm32_transfer_begin()
1184 data->status_fifo = k_heap_alloc(&stm32_i3c_fifo_heap, data->fifo_len, K_FOREVER); in i3c_stm32_transfer_begin()
1188 for (size_t i = 0; i < curr_msg->num_msgs; i++) { in i3c_stm32_transfer_begin()
1189 WRITE_REG(data->control_fifo[i], in i3c_stm32_transfer_begin()
1190 ((curr_msg->target_addr << I3C_CR_ADD_Pos) | in i3c_stm32_transfer_begin()
1192 i3c_stm32_curr_msg_control_get_dir(dev) | curr_msg->msg_type | in i3c_stm32_transfer_begin()
1229 if (k_sem_take(&data->device_sync_sem, STM32_I3C_TRANSFER_TIMEOUT) != 0) { in i3c_stm32_transfer_begin()
1230 return -ETIMEDOUT; in i3c_stm32_transfer_begin()
1233 if (data->msg_state == STM32_I3C_MSG_ERR) { in i3c_stm32_transfer_begin()
1234 return -EIO; in i3c_stm32_transfer_begin()
1244 struct i3c_stm32_data *data = dev->data; in i3c_stm32_i3c_transfer()
1250 return -EINVAL; in i3c_stm32_i3c_transfer()
1253 return -ENOTSUP; in i3c_stm32_i3c_transfer()
1257 k_mutex_lock(&data->bus_mutex, K_FOREVER); in i3c_stm32_i3c_transfer()
1258 ret = i3c_stm32_curr_msg_init(dev, msgs, NULL, num_msgs, target->dynamic_addr); in i3c_stm32_i3c_transfer()
1275 msgs[i].num_xfer = READ_BIT(data->status_fifo[i], I3C_SR_XDCNT); in i3c_stm32_i3c_transfer()
1278 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo); in i3c_stm32_i3c_transfer()
1279 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo); in i3c_stm32_i3c_transfer()
1284 k_mutex_unlock(&data->bus_mutex); in i3c_stm32_i3c_transfer()
1292 struct i3c_stm32_data *data = dev->data; in i3c_stm32_i2c_transfer()
1293 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_i2c_transfer()
1294 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_i2c_transfer()
1300 return -EINVAL; in i3c_stm32_i2c_transfer()
1303 LOG_ERR("10-bit addressing mode is not supported"); in i3c_stm32_i2c_transfer()
1304 return -ENOTSUP; in i3c_stm32_i2c_transfer()
1308 k_mutex_lock(&data->bus_mutex, K_FOREVER); in i3c_stm32_i2c_transfer()
1330 k_heap_free(&stm32_i3c_fifo_heap, data->control_fifo); in i3c_stm32_i2c_transfer()
1331 k_heap_free(&stm32_i3c_fifo_heap, data->status_fifo); in i3c_stm32_i2c_transfer()
1336 k_mutex_unlock(&data->bus_mutex); in i3c_stm32_i2c_transfer()
1345 const struct i3c_stm32_config *cfg = dev->config; in i3c_stm32_suspend()
1349 ret = clock_control_off(clk, (clock_control_subsys_t)&cfg->pclken[0]); in i3c_stm32_suspend()
1356 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_SLEEP); in i3c_stm32_suspend()
1357 if (ret == -ENOENT) { in i3c_stm32_suspend()
1379 return -ENOTSUP; in i3c_stm32_pm_action()
1391 if (dma_stream->dma_dev != NULL) { in i3c_stm32_dma_stream_config()
1392 if (!device_is_ready(dma_stream->dma_dev)) { in i3c_stm32_dma_stream_config()
1393 return -ENODEV; in i3c_stm32_dma_stream_config()
1397 memset(&dma_stream->blk_cfg, 0, sizeof(dma_stream->blk_cfg)); in i3c_stm32_dma_stream_config()
1399 dma_stream->blk_cfg.source_address = src_addr; in i3c_stm32_dma_stream_config()
1401 dma_stream->blk_cfg.dest_address = dst_addr; in i3c_stm32_dma_stream_config()
1403 if (dma_stream->src_addr_increment) { in i3c_stm32_dma_stream_config()
1404 dma_stream->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_INCREMENT; in i3c_stm32_dma_stream_config()
1406 dma_stream->blk_cfg.source_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in i3c_stm32_dma_stream_config()
1409 if (dma_stream->dst_addr_increment) { in i3c_stm32_dma_stream_config()
1410 dma_stream->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_INCREMENT; in i3c_stm32_dma_stream_config()
1412 dma_stream->blk_cfg.dest_addr_adj = DMA_ADDR_ADJ_NO_CHANGE; in i3c_stm32_dma_stream_config()
1415 dma_stream->blk_cfg.source_reload_en = 0; in i3c_stm32_dma_stream_config()
1416 dma_stream->blk_cfg.dest_reload_en = 0; in i3c_stm32_dma_stream_config()
1417 dma_stream->blk_cfg.fifo_mode_control = dma_stream->fifo_threshold; in i3c_stm32_dma_stream_config()
1419 dma_stream->dma_cfg.head_block = &dma_stream->blk_cfg; in i3c_stm32_dma_stream_config()
1420 dma_stream->dma_cfg.user_data = (void *)dev; in i3c_stm32_dma_stream_config()
1428 struct i3c_stm32_data *data = dev->data; in i3c_stm32_init_dma()
1430 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_init_dma()
1431 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_init_dma()
1435 dev, &data->dma_rx, LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_RECEIVE_BYTE), in i3c_stm32_init_dma()
1442 err = i3c_stm32_dma_stream_config(dev, &data->dma_rs, in i3c_stm32_init_dma()
1450 dev, &data->dma_tx, 0, in i3c_stm32_init_dma()
1457 err = i3c_stm32_dma_stream_config(dev, &data->dma_tc, 0, in i3c_stm32_init_dma()
1469 struct i3c_stm32_data *data = dev->data; in i3c_stm32_controller_init()
1470 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_controller_init()
1471 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_controller_init()
1505 data->msg_state = STM32_I3C_MSG_IDLE; in i3c_stm32_controller_init()
1506 data->sf_state = STM32_I3C_SF_IDLE; in i3c_stm32_controller_init()
1507 data->target_id = 0; in i3c_stm32_controller_init()
1509 data->ibi_payload = 0; in i3c_stm32_controller_init()
1510 data->ibi_payload_size = 0; in i3c_stm32_controller_init()
1511 data->ibi_target_addr = 0; in i3c_stm32_controller_init()
1518 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_init()
1519 struct i3c_stm32_data *data = dev->data; in i3c_stm32_init()
1520 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_init()
1532 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT); in i3c_stm32_init()
1538 k_mutex_init(&data->bus_mutex); in i3c_stm32_init()
1542 k_sem_init(&data->ibi_lock_sem, 1, 1); in i3c_stm32_init()
1550 config->irq_config_func(dev); in i3c_stm32_init()
1551 i3c_stm32_configure(dev, I3C_CONFIG_CONTROLLER, &data->drv_data.ctrl_config); in i3c_stm32_init()
1555 if (config->drv_cfg.dev_list.num_i3c > 0) { in i3c_stm32_init()
1556 ret = i3c_bus_init(dev, &config->drv_cfg.dev_list); in i3c_stm32_init()
1572 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_event_isr_tx()
1573 struct i3c_stm32_data *data = dev->data; in i3c_stm32_event_isr_tx()
1574 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr_tx()
1576 switch (data->msg_state) { in i3c_stm32_event_isr_tx()
1597 bcr = (data->pid >> 8) & 0xFF; in i3c_stm32_event_isr_tx()
1598 dcr = data->pid & 0xFF; in i3c_stm32_event_isr_tx()
1599 data->pid >>= 16; in i3c_stm32_event_isr_tx()
1602 ret = i3c_dev_list_daa_addr_helper(&data->drv_data.attached_dev.addr_slots, in i3c_stm32_event_isr_tx()
1603 &config->drv_cfg.dev_list, data->pid, false, in i3c_stm32_event_isr_tx()
1619 target->dynamic_addr = dyn_addr; in i3c_stm32_event_isr_tx()
1620 target->bcr = bcr; in i3c_stm32_event_isr_tx()
1621 target->dcr = dcr; in i3c_stm32_event_isr_tx()
1625 i3c_addr_slots_mark_i3c(&data->drv_data.attached_dev.addr_slots, dyn_addr); in i3c_stm32_event_isr_tx()
1628 if ((target != NULL) && (target->static_addr != 0) && in i3c_stm32_event_isr_tx()
1629 (dyn_addr != target->static_addr)) { in i3c_stm32_event_isr_tx()
1630 i3c_addr_slots_mark_free(&data->drv_data.attached_dev.addr_slots, dyn_addr); in i3c_stm32_event_isr_tx()
1636 struct i3c_ccc_payload *payload = data->ccc_payload; in i3c_stm32_event_isr_tx()
1638 if (payload->ccc.num_xfer < payload->ccc.data_len) { in i3c_stm32_event_isr_tx()
1639 LL_I3C_TransmitData8(i3c, payload->ccc.data[payload->ccc.num_xfer++]); in i3c_stm32_event_isr_tx()
1644 struct i3c_ccc_target_payload *target = data->ccc_target_payload; in i3c_stm32_event_isr_tx()
1646 if (target->num_xfer < target->data_len) { in i3c_stm32_event_isr_tx()
1647 LL_I3C_TransmitData8(i3c, target->data[target->num_xfer++]); in i3c_stm32_event_isr_tx()
1650 if (target->num_xfer == target->data_len) { in i3c_stm32_event_isr_tx()
1651 data->ccc_target_payload++; in i3c_stm32_event_isr_tx()
1663 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_event_isr_rx()
1664 struct i3c_stm32_data *data = dev->data; in i3c_stm32_event_isr_rx()
1665 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr_rx()
1667 switch (data->msg_state) { in i3c_stm32_event_isr_rx()
1681 data->pid <<= 8; in i3c_stm32_event_isr_rx()
1682 data->pid |= LL_I3C_ReceiveData8(i3c); in i3c_stm32_event_isr_rx()
1684 data->daa_rx_rcv++; in i3c_stm32_event_isr_rx()
1689 if (data->daa_rx_rcv == 8) { in i3c_stm32_event_isr_rx()
1691 data->daa_rx_rcv = 0; in i3c_stm32_event_isr_rx()
1696 struct i3c_ccc_target_payload *target = data->ccc_target_payload; in i3c_stm32_event_isr_rx()
1698 if (target->num_xfer < target->data_len) { in i3c_stm32_event_isr_rx()
1699 target->data[target->num_xfer++] = LL_I3C_ReceiveData8(i3c); in i3c_stm32_event_isr_rx()
1703 if (target->num_xfer == target->data_len) { in i3c_stm32_event_isr_rx()
1704 data->ccc_target_payload++; in i3c_stm32_event_isr_rx()
1716 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_event_isr_cf()
1717 struct i3c_stm32_data *data = dev->data; in i3c_stm32_event_isr_cf()
1718 struct i3c_stm32_msg *curr_msg = &data->curr_msg; in i3c_stm32_event_isr_cf()
1719 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr_cf()
1721 switch (data->msg_state) { in i3c_stm32_event_isr_cf()
1724 i3c, curr_msg->target_addr, i3c_stm32_curr_msg_control_get_len(dev), in i3c_stm32_event_isr_cf()
1725 i3c_stm32_curr_msg_control_get_dir(dev), curr_msg->msg_type, in i3c_stm32_event_isr_cf()
1733 struct i3c_ccc_payload *payload = data->ccc_payload; in i3c_stm32_event_isr_cf()
1736 if (data->ccc_target_idx < payload->targets.num_targets) { in i3c_stm32_event_isr_cf()
1737 target = &payload->targets.payloads[data->ccc_target_idx++]; in i3c_stm32_event_isr_cf()
1740 i3c, target->addr, target->data_len, in i3c_stm32_event_isr_cf()
1741 target->rnw ? LL_I3C_DIRECTION_READ : LL_I3C_DIRECTION_WRITE, in i3c_stm32_event_isr_cf()
1743 (data->ccc_target_idx == payload->targets.num_targets) in i3c_stm32_event_isr_cf()
1748 if (data->msg_state == STM32_I3C_MSG_CCC) { in i3c_stm32_event_isr_cf()
1749 data->msg_state = STM32_I3C_MSG_CCC_P2; in i3c_stm32_event_isr_cf()
1764 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_event_isr()
1765 struct i3c_stm32_data *data = dev->data; in i3c_stm32_event_isr()
1766 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr()
1786 if (data->msg_state == STM32_I3C_MSG) { in i3c_stm32_event_isr()
1793 uint32_t status_reg = i3c->SR; in i3c_stm32_event_isr()
1804 data->ccc_target_payload++; in i3c_stm32_event_isr()
1811 k_sem_give(&data->device_sync_sem); in i3c_stm32_event_isr()
1817 data->msg_state = STM32_I3C_MSG_IDLE; in i3c_stm32_event_isr()
1822 k_sem_take(&data->ibi_lock_sem, K_FOREVER); in i3c_stm32_event_isr()
1827 data->ibi_payload = LL_I3C_GetIBIPayload(i3c); in i3c_stm32_event_isr()
1828 data->ibi_payload_size = LL_I3C_GetNbIBIAddData(i3c); in i3c_stm32_event_isr()
1829 data->ibi_target_addr = LL_I3C_GetIBITargetAddr(i3c); in i3c_stm32_event_isr()
1830 if ((data->ibi_payload == 0) && (data->ibi_payload_size == 0) && in i3c_stm32_event_isr()
1831 (data->ibi_target_addr == 0)) { in i3c_stm32_event_isr()
1834 LOG_INF("IBI done, payload received :%d,%d,%d\n", data->ibi_payload, in i3c_stm32_event_isr()
1835 data->ibi_payload_size, data->ibi_target_addr); in i3c_stm32_event_isr()
1836 if ((data->ibi_payload != 0) && (data->ibi_payload_size != 0)) { in i3c_stm32_event_isr()
1839 target = i3c_dev_list_i3c_addr_find(dev, data->ibi_target_addr); in i3c_stm32_event_isr()
1843 target, (uint8_t *)&data->ibi_payload, in i3c_stm32_event_isr()
1844 data->ibi_payload_size) != 0) { in i3c_stm32_event_isr()
1849 data->ibi_target_addr); in i3c_stm32_event_isr()
1866 k_sem_give(&data->ibi_lock_sem); in i3c_stm32_event_isr()
1880 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_error_isr()
1881 struct i3c_stm32_data *data = dev->data; in i3c_stm32_error_isr()
1882 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_error_isr()
1888 data->msg_state = STM32_I3C_MSG_ERR; in i3c_stm32_error_isr()
1890 k_sem_give(&data->device_sync_sem); in i3c_stm32_error_isr()
1904 struct i3c_stm32_data *data = dev->data; in i3c_stm32_ibi_enable()
1905 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_ibi_enable()
1907 i3c = config->i3c; in i3c_stm32_ibi_enable()
1909 return -EINVAL; in i3c_stm32_ibi_enable()
1912 if (data->ibi.num_addr >= ARRAY_SIZE(data->ibi.addr)) { in i3c_stm32_ibi_enable()
1915 return -ENOMEM; in i3c_stm32_ibi_enable()
1918 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) { in i3c_stm32_ibi_enable()
1919 if (data->ibi.addr[idx] == target->dynamic_addr) { in i3c_stm32_ibi_enable()
1921 return -EINVAL; in i3c_stm32_ibi_enable()
1925 if (data->ibi.num_addr > 0) { in i3c_stm32_ibi_enable()
1926 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) { in i3c_stm32_ibi_enable()
1927 if (data->ibi.addr[idx] == 0U) { in i3c_stm32_ibi_enable()
1932 if (idx >= ARRAY_SIZE(data->ibi.addr)) { in i3c_stm32_ibi_enable()
1934 return -ENOTSUP; in i3c_stm32_ibi_enable()
1941 data->ibi.addr[idx] = target->dynamic_addr; in i3c_stm32_ibi_enable()
1942 data->ibi.num_addr += 1U; in i3c_stm32_ibi_enable()
1944 if (data->ibi.num_addr == 1U) { in i3c_stm32_ibi_enable()
1952 LOG_ERR("Error sending IBI ENEC for 0x%02x (%d)", target->dynamic_addr, ret); in i3c_stm32_ibi_enable()
1956 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr, in i3c_stm32_ibi_enable()
1971 struct i3c_stm32_data *data = dev->data; in i3c_stm32_ibi_disable()
1972 const struct i3c_stm32_config *config = dev->config; in i3c_stm32_ibi_disable()
1974 i3c = config->i3c; in i3c_stm32_ibi_disable()
1976 return -EINVAL; in i3c_stm32_ibi_disable()
1979 for (idx = 0; idx < ARRAY_SIZE(data->ibi.addr); idx++) { in i3c_stm32_ibi_disable()
1980 if (target->dynamic_addr == data->ibi.addr[idx]) { in i3c_stm32_ibi_disable()
1985 if (idx == ARRAY_SIZE(data->ibi.addr)) { in i3c_stm32_ibi_disable()
1987 return -ENODEV; in i3c_stm32_ibi_disable()
1990 data->ibi.addr[idx] = 0U; in i3c_stm32_ibi_disable()
1991 data->ibi.num_addr -= 1U; in i3c_stm32_ibi_disable()
1993 if (data->ibi.num_addr == 0U) { in i3c_stm32_ibi_disable()
2001 LOG_ERR("Error sending IBI DISEC for 0x%02x (%d)", target->dynamic_addr, ret); in i3c_stm32_ibi_disable()
2005 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr, in i3c_stm32_ibi_disable()