Lines Matching full:i3c
8 #include <zephyr/drivers/i3c.h>
114 struct i3c_driver_config drv_cfg; /* I3C driver config */
115 I3C_TypeDef *i3c; /* Pointer to I3C module base addr */ member
122 struct i3c_driver_data drv_data; /* I3C driver data */
123 enum i3c_stm32_msg_state msg_state; /* Current I3C bus state */
124 enum i3c_stm32_sf_state sf_state; /* Current I3C status FIFO state */
163 * Determine I3C bus mode from the i2c devices on the bus.
165 * Reads the LVR of all I2C devices and returns the I3C bus
226 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_arbitration_header_config() local
231 LL_I3C_DisableArbitrationHeader(i3c); in i3c_stm32_arbitration_header_config()
234 LL_I3C_EnableArbitrationHeader(i3c); in i3c_stm32_arbitration_header_config()
257 /* I3C private message */ in i3c_stm32_curr_msg_init()
431 /* Activates the device I3C pinctrl and CLK */
465 "current I3C clock " in i3c_stm32_calc_scll_od_sclh_i2c()
479 LOG_ERR("Cannot find a combination of SCLL_OD and SCLH_I2C at current I3C " in i3c_stm32_calc_scll_od_sclh_i2c()
513 "SCLH_I2C at current I3C clock " in i3c_stm32_calc_scll_od_sclh_i2c()
524 "at current I3C clock " in i3c_stm32_calc_scll_od_sclh_i2c()
551 LOG_ERR("Cannot find a combination of SCLL_PP and SCLH_I3C at current I3C clock " in i3c_stm32_calc_scll_pp_sclh_i3c()
552 "frequency for specified I3C bus speed"); in i3c_stm32_calc_scll_pp_sclh_i3c()
565 I3C_TypeDef *i3c = cfg->i3c; in i3c_stm32_config_clk_wave() local
568 uint32_t i3c_bus_freq = data->drv_data.ctrl_config.scl.i3c; in i3c_stm32_config_clk_wave()
582 LOG_DBG("I3C Clock = %u, I2C Bus Freq = %u, I3C Bus Freq = %u", i3c_clock, i2c_bus_freq, in i3c_stm32_config_clk_wave()
602 LL_I3C_ConfigClockWaveForm(i3c, clk_wave); in i3c_stm32_config_clk_wave()
607 * @brief Get current configuration of the I3C hardware.
635 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_config_ctrl_bus_char() local
648 /* Satisfying I3C start timing min timing will statisfy the rest of the conditions */ in i3c_stm32_config_ctrl_bus_char()
682 /* Pure I3C bus */ in i3c_stm32_config_ctrl_bus_char()
690 LL_I3C_SetFreeTiming(i3c, free_timing); in i3c_stm32_config_ctrl_bus_char()
691 LL_I3C_SetAvalTiming(i3c, aval); in i3c_stm32_config_ctrl_bus_char()
692 LL_I3C_SetDataHoldTime(i3c, LL_I3C_SDA_HOLD_TIME_1_5); in i3c_stm32_config_ctrl_bus_char()
694 LOG_DBG("TimingReg1 = 0x%08x", LL_I3C_GetCtrlBusCharacteristic(i3c)); in i3c_stm32_config_ctrl_bus_char()
699 /* Configures the I3C module in controller mode */
711 if ((ctrl_cfg->scl.i2c == 0U) || (ctrl_cfg->scl.i3c == 0U)) { in i3c_stm32_configure()
715 data->drv_data.ctrl_config.scl.i3c = ctrl_cfg->scl.i3c; in i3c_stm32_configure()
720 LOG_ERR("Clock and GPIO could not be initialized for the I3C module, err=%d", ret); in i3c_stm32_configure()
759 * @brief Find a registered I3C target device.
761 * This returns the I3C device descriptor of the I3C device
765 * @param id Pointer to I3C device ID.
782 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_end_dma_requests() local
784 LL_I3C_EnableIT_TXFNF(i3c); in i3c_stm32_end_dma_requests()
785 LL_I3C_EnableIT_RXFNE(i3c); in i3c_stm32_end_dma_requests()
786 LL_I3C_EnableIT_CFNF(i3c); in i3c_stm32_end_dma_requests()
787 LL_I3C_EnableIT_SFNE(i3c); in i3c_stm32_end_dma_requests()
789 LL_I3C_DisableDMAReq_TX(i3c); in i3c_stm32_end_dma_requests()
790 LL_I3C_DisableDMAReq_RX(i3c); in i3c_stm32_end_dma_requests()
791 LL_I3C_DisableDMAReq_Control(i3c); in i3c_stm32_end_dma_requests()
792 LL_I3C_DisableDMAReq_Status(i3c); in i3c_stm32_end_dma_requests()
798 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_prepare_dma_requests() local
800 LL_I3C_DisableIT_TXFNF(i3c); in i3c_stm32_prepare_dma_requests()
801 LL_I3C_DisableIT_RXFNE(i3c); in i3c_stm32_prepare_dma_requests()
802 LL_I3C_DisableIT_CFNF(i3c); in i3c_stm32_prepare_dma_requests()
803 LL_I3C_DisableIT_SFNE(i3c); in i3c_stm32_prepare_dma_requests()
805 LL_I3C_EnableDMAReq_TX(i3c); in i3c_stm32_prepare_dma_requests()
806 LL_I3C_EnableDMAReq_RX(i3c); in i3c_stm32_prepare_dma_requests()
807 LL_I3C_EnableDMAReq_Control(i3c); in i3c_stm32_prepare_dma_requests()
808 LL_I3C_EnableDMAReq_Status(i3c); in i3c_stm32_prepare_dma_requests()
816 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_flush_all_fifo() local
818 LL_I3C_RequestTxFIFOFlush(i3c); in i3c_stm32_flush_all_fifo()
819 LL_I3C_RequestRxFIFOFlush(i3c); in i3c_stm32_flush_all_fifo()
820 LL_I3C_RequestControlFIFOFlush(i3c); in i3c_stm32_flush_all_fifo()
821 LL_I3C_RequestStatusFIFOFlush(i3c); in i3c_stm32_flush_all_fifo()
827 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_log_err_type() local
829 if (LL_I3C_IsActiveFlag_ANACK(i3c)) { in i3c_stm32_log_err_type()
833 if (LL_I3C_IsActiveFlag_COVR(i3c)) { in i3c_stm32_log_err_type()
837 if (LL_I3C_IsActiveFlag_DOVR(i3c)) { in i3c_stm32_log_err_type()
841 if (LL_I3C_IsActiveFlag_DNACK(i3c)) { in i3c_stm32_log_err_type()
845 if (LL_I3C_IsActiveFlag_PERR(i3c)) { in i3c_stm32_log_err_type()
846 switch (LL_I3C_GetMessageErrorCode(i3c)) { in i3c_stm32_log_err_type()
867 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_clear_err() local
873 LL_I3C_EnableArbitrationHeader(i3c); in i3c_stm32_clear_err()
890 * @brief Fills the I3C TX FIFO from a given buffer
903 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_fill_tx_fifo() local
910 while (LL_I3C_IsActiveFlag_TXFNF(i3c)) { in i3c_stm32_fill_tx_fifo()
911 if (LL_I3C_IsActiveFlag_TXLAST(i3c)) { in i3c_stm32_fill_tx_fifo()
916 LL_I3C_TransmitData8(i3c, buf[(*offset)++]); in i3c_stm32_fill_tx_fifo()
928 * @brief Drains the I3C RX FIFO from a given buffer
941 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_drain_rx_fifo() local
948 while (LL_I3C_IsActiveFlag_RXFNE(i3c)) { in i3c_stm32_drain_rx_fifo()
949 if (LL_I3C_IsActiveFlag_RXLAST(i3c)) { in i3c_stm32_drain_rx_fifo()
954 buf[(*offset)++] = LL_I3C_ReceiveData8(i3c); in i3c_stm32_drain_rx_fifo()
970 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_do_ccc() local
972 __ASSERT(dev != NULL, "I3C Device is NULL."); in i3c_stm32_do_ccc()
973 __ASSERT(payload != NULL, "I3C Payload is NULL."); in i3c_stm32_do_ccc()
994 LL_I3C_DisableStatusFIFO(i3c); in i3c_stm32_do_ccc()
995 LL_I3C_EnableIT_RXTGTEND(i3c); in i3c_stm32_do_ccc()
1015 LL_I3C_ControllerHandleCCC(i3c, payload->ccc.id, payload->ccc.data_len, in i3c_stm32_do_ccc()
1022 LL_I3C_DisableIT_RXTGTEND(i3c); in i3c_stm32_do_ccc()
1023 LL_I3C_EnableStatusFIFO(i3c); in i3c_stm32_do_ccc()
1029 LL_I3C_DisableIT_RXTGTEND(i3c); in i3c_stm32_do_ccc()
1030 LL_I3C_EnableStatusFIFO(i3c); in i3c_stm32_do_ccc()
1035 LL_I3C_DisableIT_RXTGTEND(i3c); in i3c_stm32_do_ccc()
1036 LL_I3C_EnableStatusFIFO(i3c); in i3c_stm32_do_ccc()
1047 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_do_daa() local
1062 LL_I3C_DisableIT_TXFNF(i3c); in i3c_stm32_do_daa()
1065 LL_I3C_ControllerHandleCCC(i3c, I3C_CCC_ENTDAA, 0, LL_I3C_GENERATE_STOP); in i3c_stm32_do_daa()
1076 LL_I3C_EnableIT_TXFNF(i3c); in i3c_stm32_do_daa()
1169 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_transfer_begin() local
1226 LL_I3C_RequestTransfer(i3c); in i3c_stm32_transfer_begin()
1294 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_i2c_transfer() local
1310 /* Disable arbitration header for all I2C messages in case no I3C devices exist on bus */ in i3c_stm32_i2c_transfer()
1311 LL_I3C_DisableArbitrationHeader(i3c); in i3c_stm32_i2c_transfer()
1327 LL_I3C_EnableArbitrationHeader(i3c); in i3c_stm32_i2c_transfer()
1351 LOG_ERR("failure disabling I3C clock"); in i3c_stm32_suspend()
1359 LOG_WRN("I3C pinctrl sleep state not available"); in i3c_stm32_suspend()
1425 /* Initializes the I3C DMA */
1431 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_init_dma() local
1435 dev, &data->dma_rx, LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_RECEIVE_BYTE), in i3c_stm32_init_dma()
1443 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_STATUS), 0); in i3c_stm32_init_dma()
1451 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_DATA_TRANSMIT_BYTE)); in i3c_stm32_init_dma()
1458 LL_I3C_DMA_GetRegAddr(i3c, LL_I3C_DMA_REG_CONTROL)); in i3c_stm32_init_dma()
1471 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_controller_init() local
1474 LL_I3C_SetRxFIFOThreshold(i3c, LL_I3C_RXFIFO_THRESHOLD_1_4); in i3c_stm32_controller_init()
1475 LL_I3C_SetTxFIFOThreshold(i3c, LL_I3C_TXFIFO_THRESHOLD_1_4); in i3c_stm32_controller_init()
1476 LL_I3C_EnableControlFIFO(i3c); in i3c_stm32_controller_init()
1477 LL_I3C_EnableStatusFIFO(i3c); in i3c_stm32_controller_init()
1479 /* I3C Initialization */ in i3c_stm32_controller_init()
1480 LL_I3C_SetMode(i3c, LL_I3C_MODE_CONTROLLER); in i3c_stm32_controller_init()
1481 LL_I3C_SetStallTime(i3c, 0x00); in i3c_stm32_controller_init()
1482 LL_I3C_DisableStallACK(i3c); in i3c_stm32_controller_init()
1483 LL_I3C_DisableStallParityCCC(i3c); in i3c_stm32_controller_init()
1484 LL_I3C_DisableStallParityData(i3c); in i3c_stm32_controller_init()
1485 LL_I3C_DisableStallTbit(i3c); in i3c_stm32_controller_init()
1486 LL_I3C_DisableHighKeeperSDA(i3c); in i3c_stm32_controller_init()
1487 LL_I3C_SetControllerActivityState(i3c, LL_I3C_OWN_ACTIVITY_STATE_0); in i3c_stm32_controller_init()
1489 LL_I3C_Enable(i3c); in i3c_stm32_controller_init()
1491 LL_I3C_EnableIT_FC(i3c); in i3c_stm32_controller_init()
1492 LL_I3C_EnableIT_CFNF(i3c); in i3c_stm32_controller_init()
1493 LL_I3C_EnableIT_SFNE(i3c); in i3c_stm32_controller_init()
1494 LL_I3C_EnableIT_RXFNE(i3c); in i3c_stm32_controller_init()
1495 LL_I3C_EnableIT_TXFNF(i3c); in i3c_stm32_controller_init()
1496 LL_I3C_EnableIT_ERR(i3c); in i3c_stm32_controller_init()
1497 LL_I3C_EnableIT_WKP(i3c); in i3c_stm32_controller_init()
1500 LL_I3C_EnableIT_IBI(i3c); in i3c_stm32_controller_init()
1501 LL_I3C_EnableIT_HJ(i3c); in i3c_stm32_controller_init()
1515 /* Initializes the I3C device and I3C bus */
1520 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_init() local
1527 LOG_ERR("Failed to init I3C DMA, err=%d", ret); in i3c_stm32_init()
1536 * atomic and has exclusive access to the I3C bus. in i3c_stm32_init()
1558 LOG_ERR("Failed to do i3c bus init, err=%d", ret); in i3c_stm32_init()
1564 LL_I3C_EnableHJAck(i3c); in i3c_stm32_init()
1574 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr_tx() local
1615 LL_I3C_TransmitData8(i3c, dyn_addr); in i3c_stm32_event_isr_tx()
1639 LL_I3C_TransmitData8(i3c, payload->ccc.data[payload->ccc.num_xfer++]); in i3c_stm32_event_isr_tx()
1647 LL_I3C_TransmitData8(i3c, target->data[target->num_xfer++]); in i3c_stm32_event_isr_tx()
1665 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr_rx() local
1682 data->pid |= LL_I3C_ReceiveData8(i3c); in i3c_stm32_event_isr_rx()
1690 LL_I3C_EnableIT_TXFNF(i3c); in i3c_stm32_event_isr_rx()
1699 target->data[target->num_xfer++] = LL_I3C_ReceiveData8(i3c); in i3c_stm32_event_isr_rx()
1719 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr_cf() local
1724 i3c, curr_msg->target_addr, i3c_stm32_curr_msg_control_get_len(dev), in i3c_stm32_event_isr_cf()
1740 i3c, target->addr, target->data_len, in i3c_stm32_event_isr_cf()
1759 /* Handles the I3C event ISR */
1766 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_event_isr() local
1769 if (LL_I3C_IsActiveFlag_TXFNF(i3c) && LL_I3C_IsEnabledIT_TXFNF(i3c)) { in i3c_stm32_event_isr()
1774 if (LL_I3C_IsActiveFlag_RXFNE(i3c) && LL_I3C_IsEnabledIT_RXFNE(i3c)) { in i3c_stm32_event_isr()
1779 if (LL_I3C_IsActiveFlag_CFNF(i3c) && LL_I3C_IsEnabledIT_CFNF(i3c)) { in i3c_stm32_event_isr()
1784 if (LL_I3C_IsActiveFlag_SFNE(i3c) && LL_I3C_IsEnabledIT_SFNE(i3c)) { in i3c_stm32_event_isr()
1787 size_t num_xfer = LL_I3C_GetXferDataCount(i3c); in i3c_stm32_event_isr()
1793 uint32_t status_reg = i3c->SR; in i3c_stm32_event_isr()
1800 if (LL_I3C_IsActiveFlag_RXTGTEND(i3c) && LL_I3C_IsEnabledIT_RXTGTEND(i3c)) { in i3c_stm32_event_isr()
1805 LL_I3C_ClearFlag_RXTGTEND(i3c); in i3c_stm32_event_isr()
1809 if (LL_I3C_IsActiveFlag_FC(i3c) && LL_I3C_IsEnabledIT_FC(i3c)) { in i3c_stm32_event_isr()
1810 LL_I3C_ClearFlag_FC(i3c); in i3c_stm32_event_isr()
1824 if (LL_I3C_IsActiveFlag_IBI(i3c)) { in i3c_stm32_event_isr()
1826 LL_I3C_ClearFlag_IBI(i3c); in i3c_stm32_event_isr()
1827 data->ibi_payload = LL_I3C_GetIBIPayload(i3c); in i3c_stm32_event_isr()
1828 data->ibi_payload_size = LL_I3C_GetNbIBIAddData(i3c); in i3c_stm32_event_isr()
1829 data->ibi_target_addr = LL_I3C_GetIBITargetAddr(i3c); in i3c_stm32_event_isr()
1855 if (LL_I3C_IsActiveFlag_HJ(i3c)) { in i3c_stm32_event_isr()
1858 LL_I3C_ClearFlag_HJ(i3c); in i3c_stm32_event_isr()
1870 if (LL_I3C_IsActiveFlag_WKP(i3c)) { in i3c_stm32_event_isr()
1871 LL_I3C_ClearFlag_WKP(i3c); in i3c_stm32_event_isr()
1875 /* Handles the I3C error ISR */
1882 I3C_TypeDef *i3c = config->i3c; in i3c_stm32_error_isr() local
1886 LL_I3C_ClearFlag_ERR(i3c); in i3c_stm32_error_isr()
1902 I3C_TypeDef *i3c; in i3c_stm32_ibi_enable() local
1907 i3c = config->i3c; in i3c_stm32_ibi_enable()
1955 /* Set I3C bus devices configuration */ in i3c_stm32_ibi_enable()
1956 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr, in i3c_stm32_ibi_enable()
1969 I3C_TypeDef *i3c; in i3c_stm32_ibi_disable() local
1974 i3c = config->i3c; in i3c_stm32_ibi_disable()
2004 /* Set I3C bus devices configuration */ in i3c_stm32_ibi_disable()
2005 LL_I3C_ConfigDeviceCapabilities(i3c, (idx + 1), target->dynamic_addr, in i3c_stm32_ibi_disable()
2058 static DEVICE_API(i3c, i3c_stm32_driver_api) = {
2152 .i3c = (I3C_TypeDef *)DT_INST_REG_ADDR(index), \
2155 .drv_cfg.dev_list.i3c = i3c_stm32_dev_arr_##index, \
2163 .drv_data.ctrl_config.scl.i3c = DT_INST_PROP_OR(index, i3c_scl_hz, 0), \