836 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_xfer_write_fifo_dma()  local
846 	mdma_inst->MDMA_TCNT1 = buf_sz;                    /* Set MDMA transfer count */  in npcx_i3c_xfer_write_fifo_dma()
847 	mdma_inst->MDMA_SRCB1 = (uint32_t)buf;             /* Set source address */  in npcx_i3c_xfer_write_fifo_dma()
848 	mdma_inst->MDMA_CTL1 |= BIT(NPCX_MDMA_CTL_MDMAEN); /* Start DMA transfer */  in npcx_i3c_xfer_write_fifo_dma()
858 	if (!IS_BIT_SET(mdma_inst->MDMA_CTL1, NPCX_MDMA_CTL_TC)) {  in npcx_i3c_xfer_write_fifo_dma()
859 		LOG_DBG("DMA busy, TC=%d", IS_BIT_SET(mdma_inst->MDMA_CTL1, NPCX_MDMA_CTL_TC));  in npcx_i3c_xfer_write_fifo_dma()
864 	mdma_inst->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_TC); /* Clear TC, W0C */  in npcx_i3c_xfer_write_fifo_dma()
865 	ret = buf_sz - mdma_inst->MDMA_CTCNT1;          /* Set transferred count */  in npcx_i3c_xfer_write_fifo_dma()
894 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_xfer_read_fifo_dma()  local
903 	mdma_inst->MDMA_TCNT0 = buf_sz;                    /* Set MDMA transfer count */  in npcx_i3c_xfer_read_fifo_dma()
904 	mdma_inst->MDMA_DSTB0 = (uint32_t)buf;             /* Set destination address */  in npcx_i3c_xfer_read_fifo_dma()
905 	mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_SIEN);   /* Enable stop interrupt */  in npcx_i3c_xfer_read_fifo_dma()
906 	mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN); /* Start DMA transfer */  in npcx_i3c_xfer_read_fifo_dma()
913 		ret = buf_sz - mdma_inst->MDMA_CTCNT0; /* Set transferred count */  in npcx_i3c_xfer_read_fifo_dma()
917 	mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_SIEN); /* Disable stop interrupt */  in npcx_i3c_xfer_read_fifo_dma()
2022 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_get_mdmafb_count()  local
2024 	if (mdma_inst->MDMA_CTCNT0 < mdma_inst->MDMA_TCNT0) {  in npcx_i3c_target_get_mdmafb_count()
2025 		return (mdma_inst->MDMA_TCNT0 - mdma_inst->MDMA_CTCNT0);  in npcx_i3c_target_get_mdmafb_count()
2034 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_get_mdmatb_count()  local
2036 	if (mdma_inst->MDMA_CTCNT1 < mdma_inst->MDMA_TCNT1) {  in npcx_i3c_target_get_mdmatb_count()
2037 		return (mdma_inst->MDMA_TCNT1 - mdma_inst->MDMA_CTCNT1);  in npcx_i3c_target_get_mdmatb_count()
2047 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_disable_mdmafb()  local
2049 	mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_MDMAEN);  in npcx_i3c_target_disable_mdmafb()
2050 	mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC); /* W0C */  in npcx_i3c_target_disable_mdmafb()
2051 	mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_SIEN);  in npcx_i3c_target_disable_mdmafb()
2065 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_enable_mdmafb()  local
2068 	if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_MDMAEN) != 0) {  in npcx_i3c_target_enable_mdmafb()
2069 		mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_MDMAEN);  in npcx_i3c_target_enable_mdmafb()
2081 	mdma_inst->MDMA_TCNT0 = len;                       /* Set MDMA transfer count */  in npcx_i3c_target_enable_mdmafb()
2082 	mdma_inst->MDMA_DSTB0 = (uint32_t)buf;             /* Set destination address */  in npcx_i3c_target_enable_mdmafb()
2083 	mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC);    /* W0C */  in npcx_i3c_target_enable_mdmafb()
2084 	mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_SIEN);   /* Enable stop interrupt */  in npcx_i3c_target_enable_mdmafb()
2085 	mdma_inst->MDMA_CTL0 |= BIT(NPCX_MDMA_CTL_MDMAEN); /* Start DMA transfer */  in npcx_i3c_target_enable_mdmafb()
2092 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_disable_mdmatb()  local
2094 	mdma_inst->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_MDMAEN);  in npcx_i3c_target_disable_mdmatb()
2095 	mdma_inst->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_TC); /* W0C */  in npcx_i3c_target_disable_mdmatb()
2096 	mdma_inst->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_SIEN);  in npcx_i3c_target_disable_mdmatb()
2110 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_enable_mdmatb()  local
2113 	if (IS_BIT_SET(mdma_inst->MDMA_CTL1, NPCX_MDMA_CTL_MDMAEN) != 0) {  in npcx_i3c_target_enable_mdmatb()
2114 		mdma_inst->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_MDMAEN);  in npcx_i3c_target_enable_mdmatb()
2132 	mdma_inst->MDMA_TCNT1 = len;                       /* Set MDMA transfer count */  in npcx_i3c_target_enable_mdmatb()
2133 	mdma_inst->MDMA_SRCB1 = (uint32_t)buf;             /* Set source address */  in npcx_i3c_target_enable_mdmatb()
2134 	mdma_inst->MDMA_CTL1 &= ~BIT(NPCX_MDMA_CTL_TC);    /* W0C */  in npcx_i3c_target_enable_mdmatb()
2135 	mdma_inst->MDMA_CTL1 |= BIT(NPCX_MDMA_CTL_MDMAEN); /* Start DMA transfer */  in npcx_i3c_target_enable_mdmatb()
2160 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_xfer_end_handle()  local
2198 	cur_xfer_cnt = mdma_inst->MDMA_CTCNT0;  in npcx_i3c_target_xfer_end_handle()
2203 		if (cur_xfer_cnt != mdma_inst->MDMA_CTCNT0) {  in npcx_i3c_target_xfer_end_handle()
2210 		cur_xfer_cnt = mdma_inst->MDMA_CTCNT0;  in npcx_i3c_target_xfer_end_handle()
2215 	if (cur_xfer_cnt == mdma_inst->MDMA_CTCNT0) {  in npcx_i3c_target_xfer_end_handle()
2645 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_target_isr()  local
2648 	if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_TC)) {  in npcx_i3c_target_isr()
2833 	struct mdma_reg *mdma_inst = config->mdma_base;  in npcx_i3c_isr()  local
2847 	if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_TC)) {  in npcx_i3c_isr()
2848 		mdma_inst->MDMA_CTL0 &= ~BIT(NPCX_MDMA_CTL_TC); /* W0C */  in npcx_i3c_isr()