1988 		if (GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_CTRENA) != MCONFIG_CTRENA_CAPABLE) {  in npcx_i3c_target_ibi_raise()
2406 	SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_PPBAUD, timing_cfg.ppbaud);  in npcx_i3c_freq_init()
2407 	SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_PPLOW, timing_cfg.pplow);  in npcx_i3c_freq_init()
2408 	SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_ODBAUD, timing_cfg.odbaud);  in npcx_i3c_freq_init()
2410 		inst->MCONFIG |= BIT(NPCX_I3C_MCONFIG_ODHPP);  in npcx_i3c_freq_init()
2412 		inst->MCONFIG &= ~BIT(NPCX_I3C_MCONFIG_ODHPP);  in npcx_i3c_freq_init()
2414 	SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_I2CBAUD, I3C_BUS_I2C_BAUD_RATE_FAST_MODE);  in npcx_i3c_freq_init()
2416 	LOG_DBG("ppbaud: %d", GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_PPBAUD));  in npcx_i3c_freq_init()
2417 	LOG_DBG("odbaud: %d", GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_ODBAUD));  in npcx_i3c_freq_init()
2418 	LOG_DBG("pplow: %d", GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_PPLOW));  in npcx_i3c_freq_init()
2419 	LOG_DBG("odhpp: %d", IS_BIT_SET(inst->MCONFIG, NPCX_I3C_MCONFIG_ODHPP));  in npcx_i3c_freq_init()
2420 	LOG_DBG("i2cbaud: %d", GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_I2CBAUD));  in npcx_i3c_freq_init()
2447 	SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_HKEEP, MCONFIG_HKEEP_EXT_SDA_SCL);  in npcx_i3c_apply_cntlr_config()
2449 	inst->MCONFIG |= BIT(NPCX_I3C_MCONFIG_ODSTOP);  in npcx_i3c_apply_cntlr_config()
2451 	inst->MCONFIG &= ~BIT(NPCX_I3C_MCONFIG_DISTO);  in npcx_i3c_apply_cntlr_config()
2559 			SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_CTRENA, MCONFIG_CTRENA_CAPABLE);  in npcx_i3c_dev_init()
2564 			SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_CTRENA, MCONFIG_CTRENA_ON);  in npcx_i3c_dev_init()
2568 		SET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_CTRENA,  in npcx_i3c_dev_init()
2937 	if (GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_CTRENA) == MCONFIG_CTRENA_ON) {  in npcx_i3c_init()
2954 	    GET_FIELD(inst->MCONFIG, NPCX_I3C_MCONFIG_CTRENA) == MCONFIG_CTRENA_ON) {  in npcx_i3c_init()