322 	if (WAIT_FOR(IS_BIT_SET(inst->MSTATUS, bit_offset), NPCX_I3C_CHK_TIMEOUT_US, NULL) ==  in npcx_i3c_status_wait_clear()
374 	if (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_ERRWARN)) {  in npcx_i3c_has_error()
418 	if (IS_BIT_SET(inst->MERRWARN, NPCX_I3C_MERRWARN_INVERQ)) {  in npcx_i3c_send_request()
512 	if (IS_BIT_SET(inst->MERRWARN, NPCX_I3C_MERRWARN_NACK)) {  in npcx_i3c_request_emit_start()
680 	while (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_TGTSTART)) {  in npcx_i3c_recover_bus()
686 		if (WAIT_FOR(IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_COMPLETE),  in npcx_i3c_recover_bus()
692 		while (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_RXPEND)) {  in npcx_i3c_recover_bus()
744 		if (WAIT_FOR(!IS_BIT_SET(inst->MDATACTRL, NPCX_I3C_MDATACTRL_TXFULL),  in npcx_i3c_xfer_write_fifo()
783 		if (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_COMPLETE)) {  in npcx_i3c_xfer_read_fifo()
790 			if (IS_BIT_SET(inst->MERRWARN, NPCX_I3C_MERRWARN_TIMEOUT)) {  in npcx_i3c_xfer_read_fifo()
800 		if (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_RXPEND)) {  in npcx_i3c_xfer_read_fifo()
858 	if (!IS_BIT_SET(mdma_inst->MDMA_CTL1, NPCX_MDMA_CTL_TC)) {  in npcx_i3c_xfer_write_fifo_dma()
859 		LOG_DBG("DMA busy, TC=%d", IS_BIT_SET(mdma_inst->MDMA_CTL1, NPCX_MDMA_CTL_TC));  in npcx_i3c_xfer_write_fifo_dma()
1077 		if (WAIT_FOR(IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_COMPLETE),  in npcx_i3c_do_one_xfer()
1371 		    IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_BETWEEN)) {  in npcx_i3c_do_daa()
1437 			if (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_NACKED)) {  in npcx_i3c_do_daa()
1455 	} while ((!IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_COMPLETE)) &&  in npcx_i3c_do_daa()
1555 	if (WAIT_FOR(IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_COMPLETE), NPCX_I3C_CHK_TIMEOUT_US,  in npcx_i3c_do_ccc()
1639 	if (WAIT_FOR(IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_IBIWON), NPCX_I3C_CHK_TIMEOUT_US,  in npcx_i3c_ibi_work()
1938 	if (!IS_BIT_SET(inst->CONFIG, NPCX_I3C_CONFIG_TGTENA) ||  in npcx_i3c_target_ibi_raise()
1939 	    IS_BIT_SET(inst->STATUS, NPCX_I3C_STATUS_STHDR)) {  in npcx_i3c_target_ibi_raise()
1945 		if (IS_BIT_SET(inst->STATUS, NPCX_I3C_STATUS_IBIDIS)) {  in npcx_i3c_target_ibi_raise()
1981 		if (IS_BIT_SET(inst->STATUS, NPCX_I3C_STATUS_MRDIS)) {  in npcx_i3c_target_ibi_raise()
1999 		if (IS_BIT_SET(inst->STATUS, NPCX_I3C_STATUS_HJDIS)) {  in npcx_i3c_target_ibi_raise()
2068 	if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_MDMAEN) != 0) {  in npcx_i3c_target_enable_mdmafb()
2113 	if (IS_BIT_SET(mdma_inst->MDMA_CTL1, NPCX_MDMA_CTL_MDMAEN) != 0) {  in npcx_i3c_target_enable_mdmatb()
2162 	bool is_i3c_start = IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_START);  in npcx_i3c_target_xfer_end_handle()
2163 	bool is_i3c_stop = IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_STOP);  in npcx_i3c_target_xfer_end_handle()
2419 	LOG_DBG("odhpp: %d", IS_BIT_SET(inst->MCONFIG, NPCX_I3C_MCONFIG_ODHPP));  in npcx_i3c_freq_init()
2648 	if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_TC)) {  in npcx_i3c_target_isr()
2672 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_STOP)) {  in npcx_i3c_target_isr()
2674 			if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_START)) {  in npcx_i3c_target_isr()
2706 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_START)) {  in npcx_i3c_target_isr()
2718 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_TGTRST)) {  in npcx_i3c_target_isr()
2723 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_ERRWARN)) {  in npcx_i3c_target_isr()
2729 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_MATCHED)) {  in npcx_i3c_target_isr()
2732 				if (IS_BIT_SET(inst->STATUS, NPCX_I3C_STATUS_STREQRD)) {  in npcx_i3c_target_isr()
2767 			if (IS_BIT_SET(inst->CONFIG, NPCX_I3C_CONFIG_MATCHSS)) {  in npcx_i3c_target_isr()
2775 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_DACHG)) {  in npcx_i3c_target_isr()
2778 			if (IS_BIT_SET(inst->DYNADDR, NPCX_I3C_DYNADDR_DAVALID)) {  in npcx_i3c_target_isr()
2787 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_CCC)) {  in npcx_i3c_target_isr()
2792 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_HDRMATCH)) {  in npcx_i3c_target_isr()
2797 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_CHANDLED)) {  in npcx_i3c_target_isr()
2802 		if (IS_BIT_SET(inst->INTMASKED, NPCX_I3C_INTMASKED_EVENT)) {  in npcx_i3c_target_isr()
2816 	if (IS_BIT_SET(inst->MINTMASKED, NPCX_I3C_MINTMASKED_NOWCNTLR)) {  in npcx_i3c_target_isr()
2827 	if (IS_BIT_SET(inst->CONFIG, NPCX_I3C_CONFIG_TGTENA)) {  in npcx_i3c_isr()
2836 	if (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_COMPLETE)) {  in npcx_i3c_isr()
2847 	if (IS_BIT_SET(mdma_inst->MDMA_CTL0, NPCX_MDMA_CTL_TC)) {  in npcx_i3c_isr()
2862 	if (IS_BIT_SET(inst->MSTATUS, NPCX_I3C_MSTATUS_TGTSTART)) {  in npcx_i3c_isr()
2999 		    IS_BIT_SET(DT_INST_PROP_BY_IDX(id, prop, 0), 0), (0))