Lines Matching refs:index
990 #define I2S_DMA_CHANNEL_INIT(index, dir, dir_cap, src_dev, dest_dev) \ argument
992 .dev_dma = DEVICE_DT_GET(STM32_DMA_CTLR(index, dir)), \
993 .dma_channel = DT_INST_DMAS_CELL_BY_NAME(index, dir, channel), \
996 .dma_slot = STM32_DMA_SLOT(index, dir, slot),\
1003 STM32_DMA_CHANNEL_CONFIG(index, dir)),\
1007 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
1009 STM32_DMA_CHANNEL_CONFIG(index, dir)), \
1011 STM32_DMA_FEATURES(index, dir)), \
1015 .mem_block_queue.buf = dir##_##index##_ring_buf, \
1016 .mem_block_queue.len = ARRAY_SIZE(dir##_##index##_ring_buf) \
1019 #define I2S_STM32_INIT(index) \ argument
1021 static void i2s_stm32_irq_config_func_##index(const struct device *dev);\
1023 PINCTRL_DT_INST_DEFINE(index); \
1025 static const struct stm32_pclken clk_##index[] = \
1026 STM32_DT_INST_CLOCKS(index); \
1028 static const struct i2s_stm32_cfg i2s_stm32_config_##index = { \
1029 .i2s = (SPI_TypeDef *)DT_INST_REG_ADDR(index), \
1030 .pclken = clk_##index, \
1031 .pclk_len = DT_INST_NUM_CLOCKS(index), \
1032 .pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(index), \
1033 .irq_config = i2s_stm32_irq_config_func_##index, \
1034 .master_clk_sel = DT_INST_PROP(index, mck_enabled) \
1037 struct queue_item rx_##index##_ring_buf[CONFIG_I2S_STM32_RX_BLOCK_COUNT + 1];\
1038 struct queue_item tx_##index##_ring_buf[CONFIG_I2S_STM32_TX_BLOCK_COUNT + 1];\
1040 static struct i2s_stm32_data i2s_stm32_data_##index = { \
1041 UTIL_AND(DT_INST_DMAS_HAS_NAME(index, rx), \
1042 I2S_DMA_CHANNEL_INIT(index, rx, RX, PERIPHERAL, MEMORY)),\
1043 UTIL_AND(DT_INST_DMAS_HAS_NAME(index, tx), \
1044 I2S_DMA_CHANNEL_INIT(index, tx, TX, MEMORY, PERIPHERAL)),\
1046 DEVICE_DT_INST_DEFINE(index, \
1048 &i2s_stm32_data_##index, \
1049 &i2s_stm32_config_##index, POST_KERNEL, \
1052 static void i2s_stm32_irq_config_func_##index(const struct device *dev) \
1054 IRQ_CONNECT(DT_INST_IRQN(index), \
1055 DT_INST_IRQ(index, priority), \
1056 i2s_stm32_isr, DEVICE_DT_INST_GET(index), 0); \
1057 irq_enable(DT_INST_IRQN(index)); \