Lines Matching refs:i2s

176 	LL_I2S_SetPrescalerLinear(cfg->i2s, i2s_div);  in i2s_stm32_set_clock()
177 LL_I2S_SetPrescalerParity(cfg->i2s, i2s_odd); in i2s_stm32_set_clock()
259 LL_I2S_EnableMasterClock(cfg->i2s); in i2s_stm32_configure()
261 LL_I2S_DisableMasterClock(cfg->i2s); in i2s_stm32_configure()
269 LL_I2S_SetDataFormat(cfg->i2s, LL_I2S_DATAFORMAT_16B); in i2s_stm32_configure()
271 LL_I2S_SetDataFormat(cfg->i2s, LL_I2S_DATAFORMAT_24B); in i2s_stm32_configure()
273 LL_I2S_SetDataFormat(cfg->i2s, LL_I2S_DATAFORMAT_32B); in i2s_stm32_configure()
282 LL_I2S_SetStandard(cfg->i2s, LL_I2S_STANDARD_PHILIPS); in i2s_stm32_configure()
286 LL_I2S_SetStandard(cfg->i2s, LL_I2S_STANDARD_PCM_SHORT); in i2s_stm32_configure()
290 LL_I2S_SetStandard(cfg->i2s, LL_I2S_STANDARD_PCM_LONG); in i2s_stm32_configure()
294 LL_I2S_SetStandard(cfg->i2s, LL_I2S_STANDARD_MSB); in i2s_stm32_configure()
298 LL_I2S_SetStandard(cfg->i2s, LL_I2S_STANDARD_LSB); in i2s_stm32_configure()
308 LL_I2S_SetClockPolarity(cfg->i2s, LL_I2S_POLARITY_HIGH); in i2s_stm32_configure()
310 LL_I2S_SetClockPolarity(cfg->i2s, LL_I2S_POLARITY_LOW); in i2s_stm32_configure()
364 if (ll_func_i2s_dma_busy(cfg->i2s)) { in i2s_stm32_trigger()
389 (ll_func_i2s_dma_busy(cfg->i2s))) { in i2s_stm32_trigger()
486 static DEVICE_API(i2s, i2s_stm32_driver_api) = {
592 (void *)LL_SPI_DMA_GetRxRegAddr(cfg->i2s), in dma_rx_callback()
594 (void *)LL_SPI_DMA_GetRegAddr(cfg->i2s), in dma_rx_callback()
703 (void *)LL_SPI_DMA_GetTxRegAddr(cfg->i2s), in dma_tx_callback()
705 (void *)LL_SPI_DMA_GetRegAddr(cfg->i2s), in dma_tx_callback()
728 if (LL_I2S_IsActiveFlag_OVR(cfg->i2s)) { in i2s_stm32_isr()
730 LL_I2S_ClearFlag_OVR(cfg->i2s); in i2s_stm32_isr()
734 if (LL_I2S_IsActiveFlag_UDR(cfg->i2s)) { in i2s_stm32_isr()
736 LL_I2S_ClearFlag_UDR(cfg->i2s); in i2s_stm32_isr()
804 LL_I2S_SetTransferMode(cfg->i2s, LL_I2S_MODE_MASTER_RX); in rx_stream_start()
806 LL_I2S_SetTransferMode(cfg->i2s, LL_I2S_MODE_SLAVE_RX); in rx_stream_start()
815 (void *)LL_SPI_DMA_GetRxRegAddr(cfg->i2s), in rx_stream_start()
817 (void *)LL_SPI_DMA_GetRegAddr(cfg->i2s), in rx_stream_start()
827 LL_I2S_EnableDMAReq_RX(cfg->i2s); in rx_stream_start()
830 LL_I2S_EnableIT_OVR(cfg->i2s); in rx_stream_start()
831 LL_I2S_EnableIT_UDR(cfg->i2s); in rx_stream_start()
832 LL_I2S_EnableIT_FRE(cfg->i2s); in rx_stream_start()
833 LL_I2S_Enable(cfg->i2s); in rx_stream_start()
834 LL_SPI_StartMasterTransfer(cfg->i2s); in rx_stream_start()
836 LL_I2S_EnableIT_ERR(cfg->i2s); in rx_stream_start()
837 LL_I2S_Enable(cfg->i2s); in rx_stream_start()
861 LL_I2S_SetTransferMode(cfg->i2s, LL_I2S_MODE_MASTER_TX); in tx_stream_start()
863 LL_I2S_SetTransferMode(cfg->i2s, LL_I2S_MODE_SLAVE_TX); in tx_stream_start()
873 (void *)LL_SPI_DMA_GetTxRegAddr(cfg->i2s), in tx_stream_start()
875 (void *)LL_SPI_DMA_GetRegAddr(cfg->i2s), in tx_stream_start()
884 LL_I2S_EnableDMAReq_TX(cfg->i2s); in tx_stream_start()
887 LL_I2S_EnableIT_OVR(cfg->i2s); in tx_stream_start()
888 LL_I2S_EnableIT_UDR(cfg->i2s); in tx_stream_start()
889 LL_I2S_EnableIT_FRE(cfg->i2s); in tx_stream_start()
891 LL_I2S_Enable(cfg->i2s); in tx_stream_start()
892 LL_SPI_StartMasterTransfer(cfg->i2s); in tx_stream_start()
894 LL_I2S_EnableIT_ERR(cfg->i2s); in tx_stream_start()
895 LL_I2S_Enable(cfg->i2s); in tx_stream_start()
905 LL_I2S_DisableDMAReq_RX(cfg->i2s); in rx_stream_disable()
907 LL_I2S_DisableIT_OVR(cfg->i2s); in rx_stream_disable()
908 LL_I2S_DisableIT_UDR(cfg->i2s); in rx_stream_disable()
909 LL_I2S_DisableIT_FRE(cfg->i2s); in rx_stream_disable()
911 LL_I2S_DisableIT_ERR(cfg->i2s); in rx_stream_disable()
920 LL_I2S_Disable(cfg->i2s); in rx_stream_disable()
929 LL_I2S_DisableDMAReq_TX(cfg->i2s); in tx_stream_disable()
931 LL_I2S_DisableIT_OVR(cfg->i2s); in tx_stream_disable()
932 LL_I2S_DisableIT_UDR(cfg->i2s); in tx_stream_disable()
933 LL_I2S_DisableIT_FRE(cfg->i2s); in tx_stream_disable()
935 LL_I2S_DisableIT_ERR(cfg->i2s); in tx_stream_disable()
946 LL_I2S_Disable(cfg->i2s); in tx_stream_disable()
1029 .i2s = (SPI_TypeDef *)DT_INST_REG_ADDR(index), \