Lines Matching +full:100 +full:base +full:- +full:t
1 /* SPDX-License-Identifier: Apache-2.0 */
17 #include "i2c-priv.h"
21 mem_addr_t base; member
45 sys_write32(SOFTR_KEY, config->base + REG_SOFTR); in i2c_xilinx_axi_reinit()
46 sys_write32(CR_TX_FIFO_RST, config->base + REG_CR); in i2c_xilinx_axi_reinit()
47 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_reinit()
48 sys_write32(GIE_ENABLE, config->base + REG_GIE); in i2c_xilinx_axi_reinit()
62 sys_write32(ISR_ADDR_TARGET, config->base + REG_IER); in i2c_xilinx_axi_target_setup()
63 sys_write32(cfg->address << 1, config->base + REG_ADR); in i2c_xilinx_axi_target_setup()
64 sys_write32(0, config->base + REG_RX_FIFO_PIRQ); in i2c_xilinx_axi_target_setup()
69 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_target_register()
70 struct i2c_xilinx_axi_data *data = dev->data; in i2c_xilinx_axi_target_register()
74 if (cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) { in i2c_xilinx_axi_target_register()
76 return -EOPNOTSUPP; in i2c_xilinx_axi_target_register()
79 k_mutex_lock(&data->mutex, K_FOREVER); in i2c_xilinx_axi_target_register()
80 key = k_spin_lock(&data->lock); in i2c_xilinx_axi_target_register()
82 if (data->target_cfg) { in i2c_xilinx_axi_target_register()
83 ret = -EBUSY; in i2c_xilinx_axi_target_register()
87 data->target_cfg = cfg; in i2c_xilinx_axi_target_register()
92 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_target_register()
94 k_mutex_unlock(&data->mutex); in i2c_xilinx_axi_target_register()
100 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_target_unregister()
101 struct i2c_xilinx_axi_data *data = dev->data; in i2c_xilinx_axi_target_unregister()
106 k_mutex_lock(&data->mutex, K_FOREVER); in i2c_xilinx_axi_target_unregister()
107 key = k_spin_lock(&data->lock); in i2c_xilinx_axi_target_unregister()
109 if (!data->target_cfg) { in i2c_xilinx_axi_target_unregister()
110 ret = -EINVAL; in i2c_xilinx_axi_target_unregister()
114 if (data->target_reading || data->target_writing) { in i2c_xilinx_axi_target_unregister()
115 ret = -EBUSY; in i2c_xilinx_axi_target_unregister()
119 data->target_cfg = NULL; in i2c_xilinx_axi_target_unregister()
120 sys_write32(0, config->base + REG_ADR); in i2c_xilinx_axi_target_unregister()
122 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_target_unregister()
123 int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_target_unregister()
125 sys_write32(int_enable, config->base + REG_IER); in i2c_xilinx_axi_target_unregister()
129 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_target_unregister()
131 k_mutex_unlock(&data->mutex); in i2c_xilinx_axi_target_unregister()
146 if (sys_read32(config->base + REG_SR) & SR_SRW) { in i2c_xilinx_axi_target_isr()
149 data->target_reading = true; in i2c_xilinx_axi_target_isr()
152 if ((*data->target_cfg->callbacks->read_requested)(data->target_cfg, in i2c_xilinx_axi_target_isr()
155 data->target_read_aborted = true; in i2c_xilinx_axi_target_isr()
158 sys_write32(read_byte, config->base + REG_TX_FIFO); in i2c_xilinx_axi_target_isr()
160 data->target_writing = true; in i2c_xilinx_axi_target_isr()
162 if ((*data->target_cfg->callbacks->write_requested)(data->target_cfg)) { in i2c_xilinx_axi_target_isr()
163 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
167 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_target_isr()
172 (*data->target_cfg->callbacks->stop)(data->target_cfg); in i2c_xilinx_axi_target_isr()
173 data->target_reading = false; in i2c_xilinx_axi_target_isr()
174 data->target_read_aborted = false; in i2c_xilinx_axi_target_isr()
175 data->target_writing = false; in i2c_xilinx_axi_target_isr()
177 sys_write32(CR_EN, config->base + REG_CR); in i2c_xilinx_axi_target_isr()
182 } else if (data->target_writing && (*int_status & ISR_RX_FIFO_FULL)) { in i2c_xilinx_axi_target_isr()
185 sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_target_isr()
187 if ((*data->target_cfg->callbacks->write_received)(data->target_cfg, in i2c_xilinx_axi_target_isr()
189 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_target_isr()
193 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_target_isr()
195 } else if (data->target_reading && (*int_status & ISR_TX_ERR_TARGET_COMP)) { in i2c_xilinx_axi_target_isr()
197 * Ignore TX FIFO empty so we don't write an extra byte. in i2c_xilinx_axi_target_isr()
203 } else if (data->target_reading && (*int_status & ISR_TX_FIFO_EMPTY)) { in i2c_xilinx_axi_target_isr()
207 if (!data->target_read_aborted && in i2c_xilinx_axi_target_isr()
208 (*data->target_cfg->callbacks->read_processed)(data->target_cfg, in i2c_xilinx_axi_target_isr()
211 data->target_read_aborted = true; in i2c_xilinx_axi_target_isr()
213 sys_write32(read_byte, config->base + REG_TX_FIFO); in i2c_xilinx_axi_target_isr()
220 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_isr()
221 struct i2c_xilinx_axi_data *data = dev->data; in i2c_xilinx_axi_isr()
222 const k_spinlock_key_t key = k_spin_lock(&data->lock); in i2c_xilinx_axi_isr()
223 uint32_t int_enable = sys_read32(config->base + REG_IER); in i2c_xilinx_axi_isr()
224 uint32_t int_status = sys_read32(config->base + REG_ISR) & int_enable; in i2c_xilinx_axi_isr()
227 LOG_DBG("ISR called for 0x%08" PRIxPTR ", status 0x%02x", config->base, int_status); in i2c_xilinx_axi_isr()
231 uint32_t cr = sys_read32(config->base + REG_CR); in i2c_xilinx_axi_isr()
234 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_isr()
238 if (data->target_cfg && (int_status & I2C_XILINX_AXI_TARGET_INTERRUPTS)) { in i2c_xilinx_axi_isr()
245 sys_write32(int_enable & ~int_status, config->base + REG_IER); in i2c_xilinx_axi_isr()
247 sys_write32(ints_to_clear & sys_read32(config->base + REG_ISR), config->base + REG_ISR); in i2c_xilinx_axi_isr()
249 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_isr()
251 k_event_post(&data->irq_event, int_status); in i2c_xilinx_axi_isr()
257 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_configure()
259 LOG_INF("Configuring %s at 0x%08" PRIxPTR, dev->name, config->base); in i2c_xilinx_axi_configure()
267 const k_spinlock_key_t key = k_spin_lock(&data->lock); in i2c_xilinx_axi_wait_interrupt()
268 const uint32_t int_enable = sys_read32(config->base + REG_IER) | int_mask; in i2c_xilinx_axi_wait_interrupt()
272 sys_write32(int_enable, config->base + REG_IER); in i2c_xilinx_axi_wait_interrupt()
273 k_event_clear(&data->irq_event, int_mask); in i2c_xilinx_axi_wait_interrupt()
274 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_wait_interrupt()
276 events = k_event_wait(&data->irq_event, int_mask, false, K_MSEC(100)); in i2c_xilinx_axi_wait_interrupt()
281 sys_read32(config->base + REG_SR), sys_read32(config->base + REG_ISR)); in i2c_xilinx_axi_wait_interrupt()
289 const k_spinlock_key_t key = k_spin_lock(&data->lock); in i2c_xilinx_axi_clear_interrupt()
290 const uint32_t int_status = sys_read32(config->base + REG_ISR); in i2c_xilinx_axi_clear_interrupt()
293 sys_write32(int_status & int_mask, config->base + REG_ISR); in i2c_xilinx_axi_clear_interrupt()
295 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_clear_interrupt()
304 if (!(sys_read32(config->base + REG_SR) & SR_RX_FIFO_EMPTY) && in i2c_xilinx_axi_wait_rx_full()
305 (sys_read32(config->base + REG_RX_FIFO_OCY) & RX_FIFO_OCY_MASK) + 1 >= read_bytes) { in i2c_xilinx_axi_wait_rx_full()
307 sys_read32(config->base + REG_SR), in i2c_xilinx_axi_wait_rx_full()
308 sys_read32(config->base + REG_RX_FIFO_OCY)); in i2c_xilinx_axi_wait_rx_full()
313 return -ETIMEDOUT; in i2c_xilinx_axi_wait_rx_full()
317 return -ENXIO; in i2c_xilinx_axi_wait_rx_full()
326 uint8_t *read_ptr = msg->buf; in i2c_xilinx_axi_read_nondyn()
327 uint32_t bytes_left = msg->len; in i2c_xilinx_axi_read_nondyn()
331 return -EINVAL; in i2c_xilinx_axi_read_nondyn()
341 * equals the PIRQ threshold, not when greater or equal. In the non-dynamic mode in i2c_xilinx_axi_read_nondyn()
352 * To avoid this, we only receive one byte at a time in the non-dynamic mode. in i2c_xilinx_axi_read_nondyn()
353 * Dynamic mode doesn't have this issue as it provides the RX byte count to the in i2c_xilinx_axi_read_nondyn()
356 sys_write32(0, config->base + REG_RX_FIFO_PIRQ); in i2c_xilinx_axi_read_nondyn()
358 if (msg->flags & I2C_MSG_RESTART) { in i2c_xilinx_axi_read_nondyn()
361 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_read_nondyn()
362 sys_write32((addr << 1) | I2C_MSG_READ, config->base + REG_TX_FIFO); in i2c_xilinx_axi_read_nondyn()
364 sys_write32((addr << 1) | I2C_MSG_READ, config->base + REG_TX_FIFO); in i2c_xilinx_axi_read_nondyn()
365 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_read_nondyn()
378 } else if (bytes_left == 1 && (msg->flags & I2C_MSG_STOP)) { in i2c_xilinx_axi_read_nondyn()
383 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_read_nondyn()
385 *read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_read_nondyn()
386 bytes_left--; in i2c_xilinx_axi_read_nondyn()
395 uint8_t *read_ptr = msg->buf; in i2c_xilinx_axi_read_dyn()
396 uint32_t bytes_left = msg->len; in i2c_xilinx_axi_read_dyn()
402 return -EINVAL; in i2c_xilinx_axi_read_dyn()
404 if (msg->flags & I2C_MSG_RESTART) { in i2c_xilinx_axi_read_dyn()
407 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_read_dyn()
412 sys_write32(bytes_to_read - 1, config->base + REG_RX_FIFO_PIRQ); in i2c_xilinx_axi_read_dyn()
413 sys_write32((addr << 1) | I2C_MSG_READ | TX_FIFO_START, config->base + REG_TX_FIFO); in i2c_xilinx_axi_read_dyn()
415 if (msg->flags & I2C_MSG_STOP) { in i2c_xilinx_axi_read_dyn()
418 sys_write32(len_word, config->base + REG_TX_FIFO); in i2c_xilinx_axi_read_dyn()
428 sys_write32(bytes_to_read - 1, config->base + REG_RX_FIFO_PIRQ); in i2c_xilinx_axi_read_dyn()
435 *read_ptr++ = sys_read32(config->base + REG_RX_FIFO) & RX_FIFO_DATA_MASK; in i2c_xilinx_axi_read_dyn()
436 bytes_to_read--; in i2c_xilinx_axi_read_dyn()
437 bytes_left--; in i2c_xilinx_axi_read_dyn()
452 return -ETIMEDOUT; in i2c_xilinx_axi_wait_tx_done()
456 return -EAGAIN; in i2c_xilinx_axi_wait_tx_done()
459 return -ENXIO; in i2c_xilinx_axi_wait_tx_done()
467 if (sys_read32(config->base + REG_SR) & SR_BB) { in i2c_xilinx_axi_wait_not_busy()
473 return -EBUSY; in i2c_xilinx_axi_wait_not_busy()
483 const uint8_t *write_ptr = msg->buf; in i2c_xilinx_axi_write()
484 uint32_t bytes_left = msg->len; in i2c_xilinx_axi_write()
486 uint32_t fifo_space = FIFO_SIZE - 1; /* account for address being written */ in i2c_xilinx_axi_write()
488 if (msg->flags & I2C_MSG_RESTART) { in i2c_xilinx_axi_write()
494 sys_write32(cr, config->base + REG_CR); in i2c_xilinx_axi_write()
495 sys_write32((addr << 1) | TX_FIFO_START, config->base + REG_TX_FIFO); in i2c_xilinx_axi_write()
508 const k_spinlock_key_t key = k_spin_lock(&data->lock); in i2c_xilinx_axi_write()
517 if (bytes_left == 1 && (msg->flags & I2C_MSG_STOP)) { in i2c_xilinx_axi_write()
520 sys_write32(write_word, config->base + REG_TX_FIFO); in i2c_xilinx_axi_write()
521 bytes_to_send--; in i2c_xilinx_axi_write()
522 bytes_left--; in i2c_xilinx_axi_write()
525 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_write()
539 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_transfer()
540 struct i2c_xilinx_axi_data *data = dev->data; in i2c_xilinx_axi_transfer()
543 k_mutex_lock(&data->mutex, K_FOREVER); in i2c_xilinx_axi_transfer()
555 * Reinitializing before each transfer shouldn't technically be needed, but in i2c_xilinx_axi_transfer()
561 if (msgs->flags & I2C_MSG_ADDR_10_BITS) { in i2c_xilinx_axi_transfer()
563 ret = -EOPNOTSUPP; in i2c_xilinx_axi_transfer()
566 if (msgs->flags & I2C_MSG_READ) { in i2c_xilinx_axi_transfer()
567 if (config->dyn_read_working && msgs->len <= MAX_DYNAMIC_READ_LEN) { in i2c_xilinx_axi_transfer()
575 if (!ret && (msgs->flags & I2C_MSG_STOP)) { in i2c_xilinx_axi_transfer()
582 num_msgs--; in i2c_xilinx_axi_transfer()
590 k_spinlock_key_t key = k_spin_lock(&data->lock); in i2c_xilinx_axi_transfer()
592 if (data->target_cfg) { in i2c_xilinx_axi_transfer()
593 i2c_xilinx_axi_target_setup(config, data->target_cfg); in i2c_xilinx_axi_transfer()
595 k_spin_unlock(&data->lock, key); in i2c_xilinx_axi_transfer()
599 k_mutex_unlock(&data->mutex); in i2c_xilinx_axi_transfer()
605 const struct i2c_xilinx_axi_config *config = dev->config; in i2c_xilinx_axi_init()
606 struct i2c_xilinx_axi_data *data = dev->data; in i2c_xilinx_axi_init()
609 k_event_init(&data->irq_event); in i2c_xilinx_axi_init()
610 k_mutex_init(&data->mutex); in i2c_xilinx_axi_init()
617 config->irq_config_func(dev); in i2c_xilinx_axi_init()
639 .base = DT_INST_REG_ADDR(n), \