Lines Matching +full:idle +full:- +full:timeout +full:- +full:ms
4 * SPDX-License-Identifier: Apache-2.0
15 * support for a two-wire SMBus/I2C synchronous serial interface. The following
21 * +<----------------+<----------------------+
23 * +------+ +------------+ | +------- ----+ | +------- -------+ |
24 * +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
25 * | +------+ +------------+ +------------+ Yes +---------------+ |
27 * | +-----------+ |
28 * +--------------------------------------------| WAIT_STOP |<------------+
29 * STOP is completed +-----------+ Issue STOP
35 * +<-----------------+<---------------------+
37 * +------+ +------------+ | +------- ---+ | +------- ------+ |
38 * +->| IDLE |-->| WAIT_START |--->| READ_FIFO |---+--->| READ_SUSPEND |--+
39 * | +------+ +------------+ +------------+ Yes +--------------+ |
41 * | +-----------+ |
42 * +------------------------------------------| WAIT_STOP |<--------------+
43 * STOP is completed +-----------+ Issue STOP
49 * +<----------------+<----------------------+
51 * +------+ +------------+ | +------- ----+ | +------- -------+ |
52 * +->| IDLE |-->| WAIT_START |--->| WRITE_FIFO |-+--->| WRITE_SUSPEND |--+
53 * | +------+ +------------+ +------------+ Yes +---------------+ |
55 * | +---------------------------------------------------------------+
58 * | | +<-----------------+<-----------------------+
60 * | | +--------------+ | +------- ---+ | +------- ------+ |
61 * | +--| WAIT_RESTART |--->| READ_FIFO |---+--->| READ_SUSPEND |----+
62 * | +--------------+ +-----------+ Yes +--------------+ |
64 * | +-----------+ |
65 * +-------------------------------------------| WAIT_STOP |<-------------+
66 * STOP is completed +-----------+ Issue STOP
85 /* Timeout for device should be available after reset (SMBus spec. unit:ms) */
88 /* Timeout for SCL held to low by slave device . (SMBus spec. unit:ms). */
91 /* Default maximum time we allow for an I2C transfer (unit:ms) */
138 uint8_t HLDT; /* i2c hold-time (Unit: clocks) */
139 uint8_t k1; /* k1 = SCL low-time (Unit: clocks) */
140 uint8_t k2; /* k2 = SCL high-time (Unit: clocks) */
172 ((struct smb_reg *)((const struct i2c_ctrl_config *)(dev)->config)->base)
192 inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_START); in i2c_ctrl_start()
199 inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_STOP); in i2c_ctrl_stop()
206 return IS_BIT_SET(inst->SMBCST, NPCX_SMBCST_BB); in i2c_ctrl_bus_busy()
214 inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_BNK_SEL); in i2c_ctrl_bank_sel()
216 inst->SMBCTL3 &= ~BIT(NPCX_SMBCTL3_BNK_SEL); in i2c_ctrl_bank_sel()
222 const struct i2c_ctrl_config *const config = dev->config; in i2c_ctrl_irq_enable()
225 irq_enable(config->irq); in i2c_ctrl_irq_enable()
227 irq_disable(config->irq); in i2c_ctrl_irq_enable()
237 inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_stall_scl()
239 inst->SMBCTL3 = (inst->SMBCTL3 & ~BIT(NPCX_SMBCTL3_SCL_LVL)) in i2c_ctrl_norm_stall_scl()
242 inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_stall_scl()
250 inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_free_scl()
255 inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_SCL_LVL) | BIT(NPCX_SMBCTL3_SDA_LVL); in i2c_ctrl_norm_free_scl()
257 inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_free_scl()
266 inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_stall_sda()
268 inst->SMBCTL3 = (inst->SMBCTL3 & ~BIT(NPCX_SMBCTL3_SDA_LVL)) in i2c_ctrl_norm_stall_sda()
271 inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_stall_sda()
279 inst->SMBCTL4 |= BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_free_sda()
284 inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_SDA_LVL) | BIT(NPCX_SMBCTL3_SCL_LVL); in i2c_ctrl_norm_free_sda()
286 inst->SMBCTL4 &= ~BIT(NPCX_SMBCTL4_LVL_WE); in i2c_ctrl_norm_free_sda()
294 inst->SMBSDA = data; in i2c_ctrl_fifo_write()
301 return inst->SMBSDA; in i2c_ctrl_fifo_read()
308 return NPCX_I2C_FIFO_MAX_SIZE - (inst->SMBTXF_STS & 0x3f); in i2c_ctrl_fifo_tx_avail()
315 return inst->SMBRXF_STS & 0x3f; in i2c_ctrl_fifo_rx_occupied()
324 SET_FIELD(inst->SMBRXF_CTL, NPCX_SMBRXF_CTL_RX_THR, value); in i2c_ctrl_fifo_rx_setup_threshold_nack()
331 inst->SMBRXF_CTL |= BIT(NPCX_SMBRXF_CTL_LAST); in i2c_ctrl_fifo_rx_setup_threshold_nack()
339 inst->SMBFIF_CTS |= BIT(NPCX_SMBFIF_CTS_CLR_FIFO); in i2c_ctrl_fifo_clear_status()
367 inst->SMBFIF_CTL |= BIT(NPCX_SMBFIF_CTL_FIFO_EN); in i2c_ctrl_init_module()
369 /* Enable module - before configuring CTL1 */ in i2c_ctrl_init_module()
370 inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE); in i2c_ctrl_init_module()
373 inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN); in i2c_ctrl_init_module()
382 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_config_bus_freq()
384 data->ptr_speed_confs[bus_freq]; in i2c_ctrl_config_bus_freq()
392 inst->SMBCTL3 &= ~(BIT(NPCX_SMBCTL3_400K)); in i2c_ctrl_config_bus_freq()
394 SET_FIELD(inst->SMBCTL2, NPCX_SMBCTL2_SCLFRQ0_6_FIELD, in i2c_ctrl_config_bus_freq()
396 SET_FIELD(inst->SMBCTL3, NPCX_SMBCTL3_SCLFRQ7_8_FIELD, in i2c_ctrl_config_bus_freq()
398 SET_FIELD(inst->SMBCTL4, NPCX_SMBCTL4_HLDT_FIELD, in i2c_ctrl_config_bus_freq()
402 inst->SMBCTL3 |= BIT(NPCX_SMBCTL3_400K); in i2c_ctrl_config_bus_freq()
403 /* Set high/low time of SCL and hold-time */ in i2c_ctrl_config_bus_freq()
404 inst->SMBSCLLT = bus_cfg.k1/2; in i2c_ctrl_config_bus_freq()
405 inst->SMBSCLHT = bus_cfg.k2/2; in i2c_ctrl_config_bus_freq()
406 SET_FIELD(inst->SMBCTL4, NPCX_SMBCTL4_HLDT_FIELD, in i2c_ctrl_config_bus_freq()
415 static int i2c_ctrl_wait_stop_completed(const struct device *dev, int timeout) in i2c_ctrl_wait_stop_completed() argument
419 if (timeout <= 0) { in i2c_ctrl_wait_stop_completed()
420 return -EINVAL; in i2c_ctrl_wait_stop_completed()
425 * Wait till i2c bus is idle. This bit is cleared to 0 in i2c_ctrl_wait_stop_completed()
428 if (!IS_BIT_SET(inst->SMBCTL1, NPCX_SMBCTL1_STOP)) { in i2c_ctrl_wait_stop_completed()
432 } while (--timeout); in i2c_ctrl_wait_stop_completed()
434 if (timeout > 0) { in i2c_ctrl_wait_stop_completed()
437 return -ETIMEDOUT; in i2c_ctrl_wait_stop_completed()
445 if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL) && in i2c_ctrl_is_scl_sda_both_high()
446 IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) { in i2c_ctrl_is_scl_sda_both_high()
453 static int i2c_ctrl_wait_idle_completed(const struct device *dev, int timeout) in i2c_ctrl_wait_idle_completed() argument
455 if (timeout <= 0) { in i2c_ctrl_wait_idle_completed()
456 return -EINVAL; in i2c_ctrl_wait_idle_completed()
465 } while (--timeout); in i2c_ctrl_wait_idle_completed()
467 if (timeout > 0) { in i2c_ctrl_wait_idle_completed()
470 return -ETIMEDOUT; in i2c_ctrl_wait_idle_completed()
477 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_recovery()
480 if (data->oper_state != NPCX_I2C_ERROR_RECOVERY) { in i2c_ctrl_recovery()
481 data->oper_state = NPCX_I2C_ERROR_RECOVERY; in i2c_ctrl_recovery()
489 * - Clearing NEGACK and BER bits first in i2c_ctrl_recovery()
490 * - Wait for STOP condition completed in i2c_ctrl_recovery()
491 * - Then clear BB (BUS BUSY) bit in i2c_ctrl_recovery()
493 inst->SMBST = BIT(NPCX_SMBST_BER) | BIT(NPCX_SMBST_NEGACK); in i2c_ctrl_recovery()
495 inst->SMBCST |= BIT(NPCX_SMBCST_BB); in i2c_ctrl_recovery()
498 data->port); in i2c_ctrl_recovery()
503 * - Disable the SMB module first in i2c_ctrl_recovery()
504 * - Wait both SCL/SDA line are high in i2c_ctrl_recovery()
505 * - Enable i2c module again in i2c_ctrl_recovery()
507 inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE); in i2c_ctrl_recovery()
511 data->port); in i2c_ctrl_recovery()
512 return -EIO; in i2c_ctrl_recovery()
519 data->oper_state = NPCX_I2C_IDLE; in i2c_ctrl_recovery()
525 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_notify()
527 data->trans_err = error; in i2c_ctrl_notify()
528 k_sem_give(&data->sync_sem); in i2c_ctrl_notify()
533 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_wait_completion()
535 if (k_sem_take(&data->sync_sem, I2C_TRANS_TIMEOUT) == 0) { in i2c_ctrl_wait_completion()
536 return data->trans_err; in i2c_ctrl_wait_completion()
538 return -ETIMEDOUT; in i2c_ctrl_wait_completion()
544 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_calculate_msg_remains()
545 uint8_t *buf_end = data->msg->buf + data->msg->len; in i2c_ctrl_calculate_msg_remains()
547 return (buf_end > data->ptr_msg) ? (buf_end - data->ptr_msg) : 0; in i2c_ctrl_calculate_msg_remains()
552 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_handle_write_int_event()
555 if (data->oper_state == NPCX_I2C_WAIT_START) { in i2c_ctrl_handle_write_int_event()
557 i2c_ctrl_fifo_write(dev, ((data->addr << 1) & ~BIT(0))); in i2c_ctrl_handle_write_int_event()
559 data->oper_state = NPCX_I2C_WRITE_FIFO; in i2c_ctrl_handle_write_int_event()
564 if (data->oper_state == NPCX_I2C_WRITE_FIFO) { in i2c_ctrl_handle_write_int_event()
571 i2c_ctrl_fifo_write(dev, *(data->ptr_msg++)); in i2c_ctrl_handle_write_int_event()
575 if (data->ptr_msg == data->msg->buf + data->msg->len) { in i2c_ctrl_handle_write_int_event()
576 data->oper_state = NPCX_I2C_WRITE_SUSPEND; in i2c_ctrl_handle_write_int_event()
582 if (data->oper_state == NPCX_I2C_WRITE_SUSPEND) { in i2c_ctrl_handle_write_int_event()
583 if (data->msg->flags & I2C_MSG_STOP) { in i2c_ctrl_handle_write_int_event()
589 data->oper_state = NPCX_I2C_WAIT_STOP; in i2c_ctrl_handle_write_int_event()
601 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_handle_read_int_event()
604 if (data->oper_state == NPCX_I2C_WAIT_START || in i2c_ctrl_handle_read_int_event()
605 data->oper_state == NPCX_I2C_WAIT_RESTART) { in i2c_ctrl_handle_read_int_event()
607 i2c_ctrl_fifo_rx_setup_threshold_nack(dev, data->msg->len, in i2c_ctrl_handle_read_int_event()
608 (data->msg->flags & I2C_MSG_STOP) != 0); in i2c_ctrl_handle_read_int_event()
610 i2c_ctrl_fifo_write(dev, ((data->addr << 1) | BIT(0))); in i2c_ctrl_handle_read_int_event()
612 data->oper_state = NPCX_I2C_READ_FIFO; in i2c_ctrl_handle_read_int_event()
617 if (data->oper_state == NPCX_I2C_READ_FIFO) { in i2c_ctrl_handle_read_int_event()
626 (data->msg->flags & I2C_MSG_STOP) != 0) { in i2c_ctrl_handle_read_int_event()
643 *(data->ptr_msg++) = i2c_ctrl_fifo_read(dev); in i2c_ctrl_handle_read_int_event()
650 (data->msg->flags & I2C_MSG_STOP) != 0); in i2c_ctrl_handle_read_int_event()
658 if ((data->msg->flags & I2C_MSG_STOP) != 0) { in i2c_ctrl_handle_read_int_event()
663 data->oper_state = NPCX_I2C_WAIT_STOP; in i2c_ctrl_handle_read_int_event()
667 data->oper_state = NPCX_I2C_READ_SUSPEND; in i2c_ctrl_handle_read_int_event()
676 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_proc_write_msg()
678 data->is_write = 1; in i2c_ctrl_proc_write_msg()
679 data->ptr_msg = msg->buf; in i2c_ctrl_proc_write_msg()
680 data->msg = msg; in i2c_ctrl_proc_write_msg()
682 if (data->oper_state == NPCX_I2C_IDLE) { in i2c_ctrl_proc_write_msg()
683 data->oper_state = NPCX_I2C_WAIT_START; in i2c_ctrl_proc_write_msg()
692 } else if (data->oper_state == NPCX_I2C_WRITE_SUSPEND) { in i2c_ctrl_proc_write_msg()
693 data->oper_state = NPCX_I2C_WRITE_FIFO; in i2c_ctrl_proc_write_msg()
700 data->oper_state, data->port); in i2c_ctrl_proc_write_msg()
701 data->trans_err = -EIO; in i2c_ctrl_proc_write_msg()
702 return data->trans_err; in i2c_ctrl_proc_write_msg()
707 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_proc_read_msg()
709 data->is_write = 0; in i2c_ctrl_proc_read_msg()
710 data->ptr_msg = msg->buf; in i2c_ctrl_proc_read_msg()
711 data->msg = msg; in i2c_ctrl_proc_read_msg()
713 if (data->oper_state == NPCX_I2C_IDLE) { in i2c_ctrl_proc_read_msg()
714 data->oper_state = NPCX_I2C_WAIT_START; in i2c_ctrl_proc_read_msg()
723 } else if (data->oper_state == NPCX_I2C_WRITE_SUSPEND) { in i2c_ctrl_proc_read_msg()
724 data->oper_state = NPCX_I2C_WAIT_RESTART; in i2c_ctrl_proc_read_msg()
730 } else if (data->oper_state == NPCX_I2C_READ_SUSPEND) { in i2c_ctrl_proc_read_msg()
731 data->oper_state = NPCX_I2C_READ_FIFO; in i2c_ctrl_proc_read_msg()
734 i2c_ctrl_fifo_rx_setup_threshold_nack(dev, msg->len, in i2c_ctrl_proc_read_msg()
735 (msg->flags & I2C_MSG_STOP) != 0); in i2c_ctrl_proc_read_msg()
746 data->oper_state, data->port); in i2c_ctrl_proc_read_msg()
747 data->trans_err = -EIO; in i2c_ctrl_proc_read_msg()
748 return data->trans_err; in i2c_ctrl_proc_read_msg()
756 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_target_isr()
757 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks; in i2c_ctrl_target_isr()
763 inst->SMBST = BIT(NPCX_SMBST_BER); in i2c_ctrl_target_isr()
766 if (target_cb->stop) { in i2c_ctrl_target_isr()
767 target_cb->stop(data->target_cfg); in i2c_ctrl_target_isr()
771 inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE); in i2c_ctrl_target_isr()
772 inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE); in i2c_ctrl_target_isr()
775 * Re-enable interrupts because they are turned off after the SMBus module in i2c_ctrl_target_isr()
778 inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN); in i2c_ctrl_target_isr()
780 data->oper_state = NPCX_I2C_IDLE; in i2c_ctrl_target_isr()
782 LOG_DBG("target: Bus error on port%02x!", data->port); in i2c_ctrl_target_isr()
789 inst->SMBST = BIT(NPCX_SMBST_SLVSTP); in i2c_ctrl_target_isr()
791 data->oper_state = NPCX_I2C_IDLE; in i2c_ctrl_target_isr()
793 if (target_cb->stop) { in i2c_ctrl_target_isr()
794 target_cb->stop(data->target_cfg); in i2c_ctrl_target_isr()
802 inst->SMBST = BIT(NPCX_SMBST_NEGACK); in i2c_ctrl_target_isr()
810 inst->SMBST = BIT(NPCX_SMBST_NMATCH); in i2c_ctrl_target_isr()
813 if (IS_BIT_SET(inst->SMBST, NPCX_SMBST_XMIT)) { in i2c_ctrl_target_isr()
815 data->oper_state = NPCX_I2C_WRITE_FIFO; in i2c_ctrl_target_isr()
817 if (target_cb->read_requested) { in i2c_ctrl_target_isr()
818 target_cb->read_requested(data->target_cfg, &val); in i2c_ctrl_target_isr()
820 inst->SMBSDA = val; in i2c_ctrl_target_isr()
823 data->oper_state = NPCX_I2C_READ_FIFO; in i2c_ctrl_target_isr()
825 if (target_cb->write_requested) { in i2c_ctrl_target_isr()
826 target_cb->write_requested(data->target_cfg); in i2c_ctrl_target_isr()
834 if (data->oper_state == NPCX_I2C_WRITE_FIFO) { in i2c_ctrl_target_isr()
836 if (target_cb->read_processed) { in i2c_ctrl_target_isr()
837 target_cb->read_processed(data->target_cfg, &val); in i2c_ctrl_target_isr()
839 inst->SMBSDA = val; in i2c_ctrl_target_isr()
840 } else if (data->oper_state == NPCX_I2C_READ_FIFO) { in i2c_ctrl_target_isr()
841 if (target_cb->write_received) { in i2c_ctrl_target_isr()
842 val = inst->SMBSDA; in i2c_ctrl_target_isr()
844 target_cb->write_received(data->target_cfg, val); in i2c_ctrl_target_isr()
848 data->oper_state, data->port); in i2c_ctrl_target_isr()
855 inst->SMBST = status; in i2c_ctrl_target_isr()
857 status, data->port); in i2c_ctrl_target_isr()
866 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_isr()
869 status = inst->SMBST & NPCX_VALID_SMBST_MASK; in i2c_ctrl_isr()
870 LOG_DBG("status: %02x, %d", status, data->oper_state); in i2c_ctrl_isr()
873 if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) { in i2c_ctrl_isr()
885 inst->SMBST = BIT(NPCX_SMBST_BER); in i2c_ctrl_isr()
890 LOG_ERR("Bus error occurred on i2c port%02x!", data->port); in i2c_ctrl_isr()
891 data->oper_state = NPCX_I2C_ERROR_RECOVERY; in i2c_ctrl_isr()
894 i2c_ctrl_notify(dev, -EIO); in i2c_ctrl_isr()
904 inst->SMBST = BIT(NPCX_SMBST_NEGACK); in i2c_ctrl_isr()
907 data->oper_state = NPCX_I2C_WAIT_STOP; in i2c_ctrl_isr()
910 i2c_ctrl_notify(dev, -ENXIO); in i2c_ctrl_isr()
916 if (data->is_write) { in i2c_ctrl_isr()
926 inst->SMBST = status; in i2c_ctrl_isr()
928 status, data->port); in i2c_ctrl_isr()
935 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_mutex_lock()
937 k_sem_take(&data->lock_sem, K_FOREVER); in npcx_i2c_ctrl_mutex_lock()
942 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_mutex_unlock()
944 k_sem_give(&data->lock_sem); in npcx_i2c_ctrl_mutex_unlock()
949 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_configure()
953 data->bus_freq = NPCX_I2C_BUS_SPEED_100KHZ; in npcx_i2c_ctrl_configure()
956 data->bus_freq = NPCX_I2C_BUS_SPEED_400KHZ; in npcx_i2c_ctrl_configure()
959 data->bus_freq = NPCX_I2C_BUS_SPEED_1MHZ; in npcx_i2c_ctrl_configure()
962 return -ERANGE; in npcx_i2c_ctrl_configure()
965 i2c_ctrl_config_bus_freq(i2c_dev, data->bus_freq); in npcx_i2c_ctrl_configure()
966 data->is_configured = true; in npcx_i2c_ctrl_configure()
973 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_get_speed()
975 if (!data->is_configured) { in npcx_i2c_ctrl_get_speed()
976 return -EIO; in npcx_i2c_ctrl_get_speed()
979 switch (data->bus_freq) { in npcx_i2c_ctrl_get_speed()
990 return -ERANGE; in npcx_i2c_ctrl_get_speed()
1007 if (!IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL)) { in npcx_i2c_ctrl_recover_bus()
1010 ret = -EBUSY; in npcx_i2c_ctrl_recover_bus()
1014 if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL)) { in npcx_i2c_ctrl_recover_bus()
1020 if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) { in npcx_i2c_ctrl_recover_bus()
1034 if (IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) { in npcx_i2c_ctrl_recover_bus()
1056 if (!IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SDA_LVL)) { in npcx_i2c_ctrl_recover_bus()
1058 ret = -EBUSY; in npcx_i2c_ctrl_recover_bus()
1060 if (!IS_BIT_SET(inst->SMBCTL3, NPCX_SMBCTL3_SCL_LVL)) { in npcx_i2c_ctrl_recover_bus()
1062 ret = -EBUSY; in npcx_i2c_ctrl_recover_bus()
1076 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_target_register()
1079 uint8_t addr = BIT(NPCX_SMBADDR1_SAEN) | target_cfg->address; in npcx_i2c_ctrl_target_register()
1082 if (atomic_test_and_set_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) { in npcx_i2c_ctrl_target_register()
1083 return -EBUSY; in npcx_i2c_ctrl_target_register()
1087 if (data->oper_state != NPCX_I2C_IDLE) { in npcx_i2c_ctrl_target_register()
1088 atomic_clear_bit(&data->flags, NPCX_I2C_FLAG_TARGET); in npcx_i2c_ctrl_target_register()
1089 return -EBUSY; in npcx_i2c_ctrl_target_register()
1092 data->target_cfg = target_cfg; in npcx_i2c_ctrl_target_register()
1098 inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE); in npcx_i2c_ctrl_target_register()
1099 inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE); in npcx_i2c_ctrl_target_register()
1103 inst->SMBFIF_CTL &= ~BIT(NPCX_SMBFIF_CTL_FIFO_EN); in npcx_i2c_ctrl_target_register()
1104 inst->SMBADDR1 = addr; /* Enable target mode and configure its address */ in npcx_i2c_ctrl_target_register()
1107 inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN); in npcx_i2c_ctrl_target_register()
1117 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_target_unregister()
1120 if (!atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) { in npcx_i2c_ctrl_target_unregister()
1121 return -EINVAL; in npcx_i2c_ctrl_target_unregister()
1125 if (data->oper_state != NPCX_I2C_IDLE) { in npcx_i2c_ctrl_target_unregister()
1126 return -EBUSY; in npcx_i2c_ctrl_target_unregister()
1128 data->target_cfg = NULL; in npcx_i2c_ctrl_target_unregister()
1132 inst->SMBCTL2 &= ~BIT(NPCX_SMBCTL2_ENABLE); in npcx_i2c_ctrl_target_unregister()
1133 inst->SMBCTL2 |= BIT(NPCX_SMBCTL2_ENABLE); in npcx_i2c_ctrl_target_unregister()
1135 inst->SMBADDR1 = 0; /* Disable target mode and clear address setting */ in npcx_i2c_ctrl_target_unregister()
1137 inst->SMBFIF_CTL |= BIT(NPCX_SMBFIF_CTL_FIFO_EN); in npcx_i2c_ctrl_target_unregister()
1141 inst->SMBCTL1 |= BIT(NPCX_SMBCTL1_NMINTE) | BIT(NPCX_SMBCTL1_INTEN); in npcx_i2c_ctrl_target_unregister()
1145 atomic_clear_bit(&data->flags, NPCX_I2C_FLAG_TARGET); in npcx_i2c_ctrl_target_unregister()
1154 struct i2c_ctrl_data *const data = i2c_dev->data; in npcx_i2c_ctrl_transfer()
1160 if (atomic_test_bit(&data->flags, NPCX_I2C_FLAG_TARGET)) { in npcx_i2c_ctrl_transfer()
1161 return -EBUSY; in npcx_i2c_ctrl_transfer()
1166 * suspend-to-idle stops SMB module clocks (derived from APB2/APB3), which must remain in npcx_i2c_ctrl_transfer()
1172 if (data->oper_state != NPCX_I2C_WRITE_SUSPEND && in npcx_i2c_ctrl_transfer()
1173 data->oper_state != NPCX_I2C_READ_SUSPEND) { in npcx_i2c_ctrl_transfer()
1175 data->oper_state == NPCX_I2C_ERROR_RECOVERY) { in npcx_i2c_ctrl_transfer()
1191 data->port = port; in npcx_i2c_ctrl_transfer()
1192 data->trans_err = 0; in npcx_i2c_ctrl_transfer()
1193 data->addr = addr; in npcx_i2c_ctrl_transfer()
1196 * Reset i2c event-completed semaphore before starting transactions. in npcx_i2c_ctrl_transfer()
1198 * when bus is idle. in npcx_i2c_ctrl_transfer()
1200 k_sem_reset(&data->sync_sem); in npcx_i2c_ctrl_transfer()
1206 if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_WRITE) { in npcx_i2c_ctrl_transfer()
1217 if (data->oper_state == NPCX_I2C_WAIT_STOP) { in npcx_i2c_ctrl_transfer()
1218 data->trans_err = i2c_ctrl_wait_stop_completed(i2c_dev, in npcx_i2c_ctrl_transfer()
1220 if (data->trans_err == 0) { in npcx_i2c_ctrl_transfer()
1221 data->oper_state = NPCX_I2C_IDLE; in npcx_i2c_ctrl_transfer()
1224 data->port); in npcx_i2c_ctrl_transfer()
1225 data->oper_state = NPCX_I2C_ERROR_RECOVERY; in npcx_i2c_ctrl_transfer()
1229 if (data->oper_state == NPCX_I2C_ERROR_RECOVERY || ret == -ETIMEDOUT) { in npcx_i2c_ctrl_transfer()
1248 const struct i2c_ctrl_config *const config = dev->config; in i2c_ctrl_init()
1249 struct i2c_ctrl_data *const data = dev->data; in i2c_ctrl_init()
1255 return -ENODEV; in i2c_ctrl_init()
1260 (clock_control_subsys_t) &config->clk_cfg) != 0) { in i2c_ctrl_init()
1261 LOG_ERR("Turn on %s clock fail.", dev->name); in i2c_ctrl_init()
1262 return -EIO; in i2c_ctrl_init()
1271 &config->clk_cfg, &i2c_rate) != 0) { in i2c_ctrl_init()
1272 LOG_ERR("Get %s clock rate error.", dev->name); in i2c_ctrl_init()
1273 return -EIO; in i2c_ctrl_init()
1277 data->ptr_speed_confs = npcx_15m_speed_confs; in i2c_ctrl_init()
1279 data->ptr_speed_confs = npcx_20m_speed_confs; in i2c_ctrl_init()
1281 LOG_ERR("Unsupported apb2/3 freq for %s.", dev->name); in i2c_ctrl_init()
1282 return -EIO; in i2c_ctrl_init()
1289 k_sem_init(&data->lock_sem, 1, 1); in i2c_ctrl_init()
1290 k_sem_init(&data->sync_sem, 0, K_SEM_MAX_LIMIT); in i2c_ctrl_init()
1293 data->oper_state = NPCX_I2C_IDLE; in i2c_ctrl_init()