28 #define SPEED_400KHZ_BUS	1
58 #define I2C_RPT_START		1U
61 #define I2C_ENI_EN		1U
64 #define I2C_WAIT_PIN_ASSERT	1U
68 #define I2C_XEC_STATE_STOPPED	1U
72 #define I2C_XEC_ERR_LAB		1
115  *             (16MHz/1MHz -2) = 0x05 + 0x09
177 	/* NBB -> 1 not busy can occur for STOP, BER, or LAB */  in wait_bus_free()
179 		/* No service requested(PIN=1), NotBusy(NBB=1), and no errors */  in wait_bus_free()
196  * b[0] = SCL, b[1] = SDA
237 	/* PIN=1 to clear all status except NBB and synchronize */  in i2c_xec_reset_config()
272 	 * PIN=1 clears all status except NBB  in i2c_xec_reset_config()
273 	 * ESO=1 enables output drivers  in i2c_xec_reset_config()
274 	 * ACK=1 enable ACK generation when data/address is clocked in.  in i2c_xec_reset_config()
284 	/* wait for NBB=1, BER, LAB, or timeout */  in i2c_xec_reset_config()
303  * NOTE 1: Bit-bang mode uses a HW MUX to switch the lines away from the I2C
555 	/* PIN 1->0: check for NACK */  in do_start()
611 	uint8_t addr8 = (uint8_t)((addr & 0x7FU) << 1);  in ctrl_tx()
661  * Transmitting a target address with BIT[0] == 1 causes the controller
667  * I2CSTATUS.PIN = 1, and !!generates clocks for the next
690 	uint8_t addr8 = (uint8_t)(((addr & 0x7FU) << 1) | BIT(0));  in ctrl_rx()
710 		data->read_discard = 1U;  in ctrl_rx()
720 		data->read_discard = 1U;  in ctrl_rx()
737 	uint8_t *p8 = &msg->buf[0];  in ctrl_rx()  local
743 			} else if (data_len == 1) {  in ctrl_rx()
751 			*p8++ = temp;  in ctrl_rx()
766 			*p8 = regs->I2CDATA;  in ctrl_rx()
924 			 * to catch PIN 0 -> 1 and NBB 0 -> 1.  in i2c_xec_bus_isr()
930 			 * to de-assert 0 -> 1. Data is not transmitted.  in i2c_xec_bus_isr()
950 		 * Reading I2C Data register causes PIN status 0 -> 1.  in i2c_xec_bus_isr()
1099 		.girq_pos = DT_INST_PROP_BY_IDX(n, girqs, 1),		\
1101 		.pcr_bitpos = DT_INST_PROP_BY_IDX(n, pcrs, 1),		\