Lines Matching refs:i2c
72 mxc_i2c_regs_t *i2c = cfg->regs; in max32_do_configure() local
76 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_STD_MODE); in max32_do_configure()
80 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FAST_SPEED); in max32_do_configure()
85 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_FASTPLUS_SPEED); in max32_do_configure()
91 ret = MXC_I2C_SetFrequency(i2c, MXC_I2C_HIGH_SPEED); in max32_do_configure()
111 mxc_i2c_regs_t *i2c = cfg->regs; in max32_msg_start() local
115 req->i2c = i2c; in max32_msg_start()
119 MXC_I2C_ClearRXFIFO(i2c); in max32_msg_start()
120 MXC_I2C_ClearTXFIFO(i2c); in max32_msg_start()
121 MXC_I2C_SetRXThreshold(i2c, 1); in max32_msg_start()
145 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in max32_msg_start()
146 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ERR, 0); in max32_msg_start()
147 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len); in max32_msg_start()
149 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0); in max32_msg_start()
150 MXC_I2C_Start(i2c); in max32_msg_start()
151 Wrap_MXC_I2C_WaitForRestart(i2c); in max32_msg_start()
152 MXC_I2C_WriteTXFIFO(i2c, &target_rw, 1); in max32_msg_start()
155 data->written = MXC_I2C_WriteTXFIFO(i2c, req->tx_buf, 1); in max32_msg_start()
156 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0); in max32_msg_start()
158 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0); in max32_msg_start()
163 MXC_I2C_Stop(i2c); in max32_msg_start()
182 static void i2c_max32_isr_controller(const struct device *dev, mxc_i2c_regs_t *i2c) in i2c_max32_isr_controller() argument
194 Wrap_MXC_I2C_GetIntEn(i2c, &int_en0, &int_en1); in i2c_max32_isr_controller()
195 MXC_I2C_GetFlags(i2c, &int_fl0, &int_fl1); in i2c_max32_isr_controller()
196 MXC_I2C_ClearFlags(i2c, ADI_MAX32_I2C_INT_FL0_MASK, ADI_MAX32_I2C_INT_FL1_MASK); in i2c_max32_isr_controller()
197 txfifolevel = Wrap_MXC_I2C_GetTxFIFOLevel(i2c); in i2c_max32_isr_controller()
201 Wrap_MXC_I2C_SetIntEn(i2c, 0, 0); in i2c_max32_isr_controller()
206 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0); in i2c_max32_isr_controller()
208 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0); in i2c_max32_isr_controller()
211 i2c, ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
218 written += MXC_I2C_WriteTXFIFO(i2c, &req->tx_buf[written], in i2c_max32_isr_controller()
223 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_TX_THD, 0); in i2c_max32_isr_controller()
225 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
227 Wrap_MXC_I2C_Stop(i2c); in i2c_max32_isr_controller()
234 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
239 readb += MXC_I2C_ReadRXFIFO(i2c, &req->rx_buf[readb], req->rx_len - readb); in i2c_max32_isr_controller()
241 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_RX_THD, 0); in i2c_max32_isr_controller()
243 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
244 Wrap_MXC_I2C_Stop(i2c); in i2c_max32_isr_controller()
248 MXC_I2C_DisableInt(i2c, ADI_MAX32_I2C_INT_EN0_DONE, 0); in i2c_max32_isr_controller()
254 i2c, (ADI_MAX32_I2C_INT_EN0_RX_THD | ADI_MAX32_I2C_INT_EN0_DONE), in i2c_max32_isr_controller()
256 Wrap_MXC_I2C_SetRxCount(i2c, req->rx_len - readb); in i2c_max32_isr_controller()
257 MXC_I2C_EnableInt(i2c, ADI_MAX32_I2C_INT_EN0_ADDR_ACK, 0); in i2c_max32_isr_controller()
258 i2c->fifo = (req->addr << 1) | 0x1; in i2c_max32_isr_controller()
259 Wrap_MXC_I2C_Restart(i2c); in i2c_max32_isr_controller()
343 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_isr() local
346 i2c_max32_isr_controller(dev, i2c); in i2c_max32_isr()
355 mxc_i2c_regs_t *i2c = cfg->regs; in i2c_max32_init() local
362 MXC_I2C_Shutdown(i2c); /* Clear everything out */ in i2c_max32_init()
374 ret = MXC_I2C_Init(i2c, 1, 0); /* Configure as master */ in i2c_max32_init()
379 MXC_I2C_SetFrequency(i2c, cfg->bitrate); in i2c_max32_init()