Lines Matching +full:i2c +full:- +full:command
4 * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/i2c.h>
23 #include "i2c-priv.h"
34 #define I2C_CQ_MODE_TX_MAX_PAYLOAD_SIZE (CONFIG_I2C_CQ_MODE_MAX_PAYLOAD_SIZE - 5)
39 * R/W (Read/ Write) decides the I2C read or write direction.
43 /* P (STOP) is the I2C STOP condition. */
71 /* I2C alternate configuration */
96 /* Command queue tx payload. */
98 /* Command queue rx payload. */
128 /* operation freq of i2c */
139 /* Store command queue mode messages. */
176 /* I2C interrupt enable */
186 /* Start with command queue mode */
231 struct i2c_enhance_data *data = dev->data; in i2c_parsing_return_value()
233 if (!data->err) { in i2c_parsing_return_value()
238 if (data->err == ETIMEDOUT) { in i2c_parsing_return_value()
239 return -ETIMEDOUT; in i2c_parsing_return_value()
243 if (data->err == E_HOSTA_ACK) { in i2c_parsing_return_value()
244 return -ENXIO; in i2c_parsing_return_value()
246 return -EIO; in i2c_parsing_return_value()
252 const struct i2c_enhance_config *config = dev->config; in i2c_get_line_levels()
253 uint8_t *base = config->base; in i2c_get_line_levels()
269 const struct i2c_enhance_config *config = dev->config; in i2c_is_busy()
270 uint8_t *base = config->base; in i2c_is_busy()
279 return -EIO; in i2c_bus_not_available()
287 const struct i2c_enhance_config *config = dev->config; in i2c_reset()
288 uint8_t *base = config->base; in i2c_reset()
294 /* Set clock frequency for i2c port D, E , or F */
298 const struct i2c_enhance_config *config = dev->config; in i2c_enhanced_port_set_frequency()
300 uint8_t *base = config->base; in i2c_enhanced_port_set_frequency()
301 uint8_t prescale_scl = config->prescale_scl_low; in i2c_enhanced_port_set_frequency()
311 * psr = ((pll_clock / clk_div) x (1 / freq) x (1 / 2)) - 2 in i2c_enhanced_port_set_frequency()
317 psr = (pll_clock / (clk_div * (2U * freq_hz))) - 2U; in i2c_enhanced_port_set_frequency()
336 psr_h = psr - prescale_scl; in i2c_enhanced_port_set_frequency()
339 LOG_WRN("prescale_scl_low should be less than (psr - 2)."); in i2c_enhanced_port_set_frequency()
342 /* Set I2C Speed for SCL low period. */ in i2c_enhanced_port_set_frequency()
344 /* Set I2C Speed for SCL high period. */ in i2c_enhanced_port_set_frequency()
353 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_configure()
354 struct i2c_enhance_data *const data = dev->data; in i2c_enhance_configure()
357 return -EINVAL; in i2c_enhance_configure()
361 return -EINVAL; in i2c_enhance_configure()
364 data->bus_freq = I2C_SPEED_GET(dev_config_raw); in i2c_enhance_configure()
366 i2c_enhanced_port_set_frequency(dev, config->bitrate); in i2c_enhance_configure()
373 struct i2c_enhance_data *const data = dev->data; in i2c_enhance_get_config()
376 if (!data->bus_freq) { in i2c_enhance_get_config()
378 return -EIO; in i2c_enhance_get_config()
381 switch (data->bus_freq) { in i2c_enhance_get_config()
386 speed = I2C_SPEED_SET(data->bus_freq); in i2c_enhance_get_config()
389 return -ERANGE; in i2c_enhance_get_config()
399 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_error()
400 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_error()
401 uint8_t *base = config->base; in enhanced_i2c_error()
405 data->err = i2c_str & E_HOSTA_ANY_ERROR; in enhanced_i2c_error()
409 data->err = E_HOSTA_ACK; in enhanced_i2c_error()
415 return data->err; in enhanced_i2c_error()
420 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_start()
421 uint8_t *base = config->base; in enhanced_i2c_start()
423 /* reset i2c port */ in enhanced_i2c_start()
425 /* Set i2c frequency */ in enhanced_i2c_start()
426 i2c_enhanced_port_set_frequency(dev, config->bitrate); in enhanced_i2c_start()
429 * I2C D/E/F clock/data low timeout. in enhanced_i2c_start()
432 /* bit1: Enable enhanced i2c module */ in enhanced_i2c_start()
440 struct i2c_enhance_data *data = dev->data; in i2c_pio_trans_data()
441 const struct i2c_enhance_config *config = dev->config; in i2c_pio_trans_data()
442 uint8_t *base = config->base; in i2c_pio_trans_data()
460 if (((data->ridx + 1) == data->active_msg->len) && in i2c_pio_trans_data()
461 (data->active_msg->flags & I2C_MSG_STOP)) { in i2c_pio_trans_data()
473 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_tran_read()
474 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_tran_read()
475 uint8_t *base = config->base; in enhanced_i2c_tran_read()
478 if (data->active_msg->flags & I2C_MSG_START) { in enhanced_i2c_tran_read()
480 data->active_msg->flags &= ~I2C_MSG_START; in enhanced_i2c_tran_read()
483 data->i2ccs = I2C_CH_WAIT_READ; in enhanced_i2c_tran_read()
485 i2c_pio_trans_data(dev, RX_DIRECT, data->addr_16bit << 1, 1); in enhanced_i2c_tran_read()
487 if (data->i2ccs) { in enhanced_i2c_tran_read()
488 if (data->i2ccs == I2C_CH_WAIT_READ) { in enhanced_i2c_tran_read()
489 data->i2ccs = I2C_CH_NORMAL; in enhanced_i2c_tran_read()
493 /* data->active_msg->flags == I2C_MSG_RESTART */ in enhanced_i2c_tran_read()
496 data->i2ccs = I2C_CH_WAIT_READ; in enhanced_i2c_tran_read()
499 data->addr_16bit << 1, 1); in enhanced_i2c_tran_read()
502 if (data->ridx < data->active_msg->len) { in enhanced_i2c_tran_read()
504 *(data->active_msg->buf++) = IT8XXX2_I2C_DRR(base); in enhanced_i2c_tran_read()
505 data->ridx++; in enhanced_i2c_tran_read()
507 if (data->ridx == data->active_msg->len) { in enhanced_i2c_tran_read()
508 data->active_msg->len = 0; in enhanced_i2c_tran_read()
509 if (data->active_msg->flags & I2C_MSG_STOP) { in enhanced_i2c_tran_read()
510 data->i2ccs = I2C_CH_NORMAL; in enhanced_i2c_tran_read()
513 data->stop = 1; in enhanced_i2c_tran_read()
517 data->i2ccs = I2C_CH_WAIT_READ; in enhanced_i2c_tran_read()
530 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_tran_write()
531 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_tran_write()
532 uint8_t *base = config->base; in enhanced_i2c_tran_write()
535 if (data->active_msg->flags & I2C_MSG_START) { in enhanced_i2c_tran_write()
537 data->active_msg->flags &= ~I2C_MSG_START; in enhanced_i2c_tran_write()
540 i2c_pio_trans_data(dev, TX_DIRECT, data->addr_16bit << 1, 1); in enhanced_i2c_tran_write()
543 if (data->widx < data->active_msg->len) { in enhanced_i2c_tran_write()
544 out_data = *(data->active_msg->buf++); in enhanced_i2c_tran_write()
545 data->widx++; in enhanced_i2c_tran_write()
549 if (data->i2ccs == I2C_CH_WAIT_NEXT_XFER) { in enhanced_i2c_tran_write()
550 data->i2ccs = I2C_CH_NORMAL; in enhanced_i2c_tran_write()
554 data->active_msg->len = 0; in enhanced_i2c_tran_write()
555 if (data->active_msg->flags & I2C_MSG_STOP) { in enhanced_i2c_tran_write()
558 data->stop = 1; in enhanced_i2c_tran_write()
561 data->i2ccs = I2C_CH_WAIT_NEXT_XFER; in enhanced_i2c_tran_write()
571 struct i2c_enhance_data *data = dev->data; in i2c_transaction()
572 const struct i2c_enhance_config *config = dev->config; in i2c_transaction()
573 uint8_t *base = config->base; in i2c_transaction()
577 if (!data->stop) { in i2c_transaction()
584 if (data->active_msg->flags & I2C_MSG_READ) { in i2c_transaction()
591 /* reset i2c port */ in i2c_transaction()
595 data->stop = 0; in i2c_transaction()
603 struct i2c_enhance_data *data = dev->data; in i2c_enhance_pio_transfer()
604 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_pio_transfer()
607 if (data->i2ccs == I2C_CH_NORMAL) { in i2c_enhance_pio_transfer()
610 start_msg->flags |= I2C_MSG_START; in i2c_enhance_pio_transfer()
613 for (int i = 0; i < data->num_msgs; i++) { in i2c_enhance_pio_transfer()
615 data->widx = 0; in i2c_enhance_pio_transfer()
616 data->ridx = 0; in i2c_enhance_pio_transfer()
617 data->err = 0; in i2c_enhance_pio_transfer()
618 data->active_msg = &msgs[i]; in i2c_enhance_pio_transfer()
623 * of I2C transaction for read or write has been completed. in i2c_enhance_pio_transfer()
626 /* Enable I2C interrupt. */ in i2c_enhance_pio_transfer()
627 irq_enable(config->i2c_irq_base); in i2c_enhance_pio_transfer()
630 res = k_sem_take(&data->device_sync_sem, K_MSEC(config->transfer_timeout_ms)); in i2c_enhance_pio_transfer()
633 * repeat start of I2C. If timeout occurs without being in i2c_enhance_pio_transfer()
637 irq_disable(config->i2c_irq_base); in i2c_enhance_pio_transfer()
642 if (data->err) { in i2c_enhance_pio_transfer()
647 data->err = ETIMEDOUT; in i2c_enhance_pio_transfer()
648 /* reset i2c port */ in i2c_enhance_pio_transfer()
650 LOG_ERR("I2C ch%d:0x%X reset cause %d", in i2c_enhance_pio_transfer()
651 config->port, data->addr_16bit, I2C_RC_TIMEOUT); in i2c_enhance_pio_transfer()
657 /* reset i2c channel status */ in i2c_enhance_pio_transfer()
658 if (data->err || (data->active_msg->flags & I2C_MSG_STOP)) { in i2c_enhance_pio_transfer()
659 data->i2ccs = I2C_CH_NORMAL; in i2c_enhance_pio_transfer()
662 return data->err; in i2c_enhance_pio_transfer()
668 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_set_cmd_addr_regs()
669 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_set_cmd_addr_regs()
670 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer; in enhanced_i2c_set_cmd_addr_regs()
672 uint8_t *base = config->base; in enhanced_i2c_set_cmd_addr_regs()
674 /* Set "Address Register" to store the I2C data. */ in enhanced_i2c_set_cmd_addr_regs()
675 dlm_base = (uint32_t)host_buffer->i2c_cq_mode_rx_dlm & 0xffffff; in enhanced_i2c_set_cmd_addr_regs()
680 /* Set "Command Address Register" to get commands. */ in enhanced_i2c_set_cmd_addr_regs()
681 dlm_base = (uint32_t)host_buffer->i2c_cq_mode_tx_dlm & 0xffffff; in enhanced_i2c_set_cmd_addr_regs()
689 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_cq_write()
690 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer; in enhanced_i2c_cq_write()
692 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; in enhanced_i2c_cq_write()
693 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff; in enhanced_i2c_cq_write()
695 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm; in enhanced_i2c_cq_write()
697 i2c_cq_pckt->id = data->addr_16bit << 1; in enhanced_i2c_cq_write()
698 i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_P | I2C_CQ_CMD_L_E | num_bit_2_0; in enhanced_i2c_cq_write()
699 i2c_cq_pckt->cmd_h = num_bit_10_3; in enhanced_i2c_cq_write()
700 for (int i = 0; i < data->cq_msgs[0].len; i++) { in enhanced_i2c_cq_write()
701 i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i]; in enhanced_i2c_cq_write()
707 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_cq_read()
708 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer; in enhanced_i2c_cq_read()
710 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; in enhanced_i2c_cq_read()
711 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff; in enhanced_i2c_cq_read()
713 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm; in enhanced_i2c_cq_read()
715 i2c_cq_pckt->id = data->addr_16bit << 1; in enhanced_i2c_cq_read()
716 i2c_cq_pckt->cmd_l = I2C_CQ_CMD_L_RW | I2C_CQ_CMD_L_P | in enhanced_i2c_cq_read()
718 i2c_cq_pckt->cmd_h = num_bit_10_3; in enhanced_i2c_cq_read()
723 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_cq_write_to_read()
724 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer; in enhanced_i2c_cq_write_to_read()
726 uint8_t num_bit_2_0 = (data->cq_msgs[0].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; in enhanced_i2c_cq_write_to_read()
727 uint8_t num_bit_10_3 = ((data->cq_msgs[0].len - 1) >> 3) & 0xff; in enhanced_i2c_cq_write_to_read()
730 i2c_cq_pckt = (struct i2c_cq_packet *)host_buffer->i2c_cq_mode_tx_dlm; in enhanced_i2c_cq_write_to_read()
731 /* Set commands in RAM. (command byte for write) */ in enhanced_i2c_cq_write_to_read()
732 i2c_cq_pckt->id = data->addr_16bit << 1; in enhanced_i2c_cq_write_to_read()
733 i2c_cq_pckt->cmd_l = num_bit_2_0; in enhanced_i2c_cq_write_to_read()
734 i2c_cq_pckt->cmd_h = num_bit_10_3; in enhanced_i2c_cq_write_to_read()
735 for (i = 0; i < data->cq_msgs[0].len; i++) { in enhanced_i2c_cq_write_to_read()
736 i2c_cq_pckt->wdata[i] = data->cq_msgs[0].buf[i]; in enhanced_i2c_cq_write_to_read()
739 /* Set commands in RAM. (command byte for read) */ in enhanced_i2c_cq_write_to_read()
740 num_bit_2_0 = (data->cq_msgs[1].len - 1) & I2C_CQ_CMD_L_NUM_BIT_2_0; in enhanced_i2c_cq_write_to_read()
741 num_bit_10_3 = ((data->cq_msgs[1].len - 1) >> 3) & 0xff; in enhanced_i2c_cq_write_to_read()
742 i2c_cq_pckt->wdata[i++] = I2C_CQ_CMD_L_RS | I2C_CQ_CMD_L_RW | in enhanced_i2c_cq_write_to_read()
744 i2c_cq_pckt->wdata[i] = num_bit_10_3; in enhanced_i2c_cq_write_to_read()
749 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_cq_isr()
750 struct i2c_host_cq_buffer *host_buffer = &data->host_buffer; in enhanced_i2c_cq_isr()
751 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_cq_isr()
752 uint8_t *base = config->base; in enhanced_i2c_cq_isr()
756 uint8_t msgs_idx = data->num_msgs - 1; in enhanced_i2c_cq_isr()
759 if (data->cq_msgs[msgs_idx].flags & I2C_MSG_READ) { in enhanced_i2c_cq_isr()
760 for (int i = 0; i < data->cq_msgs[msgs_idx].len; i++) { in enhanced_i2c_cq_isr()
761 data->cq_msgs[msgs_idx].buf[i] = in enhanced_i2c_cq_isr()
762 host_buffer->i2c_cq_mode_rx_dlm[i]; in enhanced_i2c_cq_isr()
768 data->err = E_HOSTA_ACK; in enhanced_i2c_cq_isr()
770 data->err = IT8XXX2_I2C_STR(base) & in enhanced_i2c_cq_isr()
783 struct i2c_enhance_data *data = dev->data; in enhanced_i2c_cmd_queue_trans()
784 const struct i2c_enhance_config *config = dev->config; in enhanced_i2c_cmd_queue_trans()
785 uint8_t *base = config->base; in enhanced_i2c_cmd_queue_trans()
789 /* Set "PSR" registers to decide the i2c speed. */ in enhanced_i2c_cmd_queue_trans()
790 i2c_enhanced_port_set_frequency(dev, config->bitrate); in enhanced_i2c_cmd_queue_trans()
794 if (data->num_msgs == 2) { in enhanced_i2c_cmd_queue_trans()
795 /* I2C write to read of command queue mode. */ in enhanced_i2c_cmd_queue_trans()
798 /* I2C read of command queue mode. */ in enhanced_i2c_cmd_queue_trans()
799 if (data->cq_msgs[0].flags & I2C_MSG_READ) { in enhanced_i2c_cmd_queue_trans()
801 /* I2C write of command queue mode. */ in enhanced_i2c_cmd_queue_trans()
807 /* Enable i2c module with command queue mode. */ in enhanced_i2c_cmd_queue_trans()
828 struct i2c_enhance_data *data = dev->data; in i2c_enhance_cq_transfer()
829 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_cq_transfer()
832 data->err = 0; in i2c_enhance_cq_transfer()
833 data->cq_msgs = msgs; in i2c_enhance_cq_transfer()
837 /* Enable i2c interrupt */ in i2c_enhance_cq_transfer()
838 irq_enable(config->i2c_irq_base); in i2c_enhance_cq_transfer()
841 res = k_sem_take(&data->device_sync_sem, K_MSEC(config->transfer_timeout_ms)); in i2c_enhance_cq_transfer()
843 irq_disable(config->i2c_irq_base); in i2c_enhance_cq_transfer()
846 data->err = ETIMEDOUT; in i2c_enhance_cq_transfer()
847 /* Reset i2c port. */ in i2c_enhance_cq_transfer()
849 LOG_ERR("I2C ch%d:0x%X reset cause %d", in i2c_enhance_cq_transfer()
850 config->port, data->addr_16bit, I2C_RC_TIMEOUT); in i2c_enhance_cq_transfer()
857 return data->err; in i2c_enhance_cq_transfer()
862 struct i2c_enhance_data *data = dev->data; in cq_mode_allowed()
866 * transfers(not two messages), the command queue mode does in cq_mode_allowed()
869 if (data->i2ccs != I2C_CH_NORMAL) { in cq_mode_allowed()
873 * When there is only one message, use the command queue transfer in cq_mode_allowed()
876 if (data->num_msgs == 1 && (msgs[0].flags & I2C_MSG_STOP)) { in cq_mode_allowed()
888 * Write of I2C target address without writing data, used by in cq_mode_allowed()
900 * do the command queue or PIO mode transfer. in cq_mode_allowed()
902 if (data->num_msgs == 2) { in cq_mode_allowed()
906 * command queue payload size, there will execute PIO mode. in cq_mode_allowed()
934 struct i2c_enhance_data *data = dev->data; in i2c_enhance_transfer()
938 if (data->target_attached) { in i2c_enhance_transfer()
940 return -EBUSY; in i2c_enhance_transfer()
943 /* Lock mutex of i2c controller */ in i2c_enhance_transfer()
944 k_mutex_lock(&data->mutex, K_FOREVER); in i2c_enhance_transfer()
946 data->num_msgs = num_msgs; in i2c_enhance_transfer()
947 data->addr_16bit = addr; in i2c_enhance_transfer()
953 if (data->i2ccs == I2C_CH_NORMAL) { in i2c_enhance_transfer()
956 /* Recovery I2C bus */ in i2c_enhance_transfer()
959 * After resetting I2C bus, if I2C bus is not available in i2c_enhance_transfer()
960 * (No external pull-up), drop the transaction. in i2c_enhance_transfer()
963 /* Unlock mutex of i2c controller */ in i2c_enhance_transfer()
964 k_mutex_unlock(&data->mutex); in i2c_enhance_transfer()
965 return -EIO; in i2c_enhance_transfer()
972 data->err = i2c_enhance_cq_transfer(dev, msgs); in i2c_enhance_transfer()
976 data->err = i2c_enhance_pio_transfer(dev, msgs); in i2c_enhance_transfer()
980 /* Unlock mutex of i2c controller */ in i2c_enhance_transfer()
981 k_mutex_unlock(&data->mutex); in i2c_enhance_transfer()
990 struct i2c_enhance_data *data = dev->data; in target_i2c_isr_dma()
991 const struct i2c_enhance_config *config = dev->config; in target_i2c_isr_dma()
992 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks; in target_i2c_isr_dma()
993 struct i2c_target_dma_buffer *target_buffer = &data->target_buffer; in target_i2c_isr_dma()
994 uint8_t *base = config->base; in target_i2c_isr_dma()
1006 target_buffer->in_buffer + in target_i2c_isr_dma()
1012 data->buffer_size = in target_i2c_isr_dma()
1017 target_cb->buf_write_received(data->target_cfg, in target_i2c_isr_dma()
1018 target_buffer->in_buffer, data->buffer_size); in target_i2c_isr_dma()
1023 target_cb->stop(data->target_cfg); in target_i2c_isr_dma()
1035 target_cb->buf_read_requested(data->target_cfg, in target_i2c_isr_dma()
1043 memcpy(target_buffer->out_buffer, rdata, len); in target_i2c_isr_dma()
1055 struct i2c_enhance_data *data = dev->data; in target_i2c_isr_pio()
1056 const struct i2c_enhance_config *config = dev->config; in target_i2c_isr_pio()
1057 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks; in target_i2c_isr_pio()
1059 uint8_t *base = config->base; in target_i2c_isr_pio()
1064 ret = target_cb->write_requested(data->target_cfg); in target_i2c_isr_pio()
1068 if (!target_cb->read_requested(data->target_cfg, &val)) { in target_i2c_isr_pio()
1077 if (!target_cb->read_processed(data->target_cfg, &val)) { in target_i2c_isr_pio()
1083 ret = target_cb->write_received(data->target_cfg, val); in target_i2c_isr_pio()
1092 struct i2c_enhance_data *data = dev->data; in target_i2c_isr()
1093 const struct i2c_enhance_config *config = dev->config; in target_i2c_isr()
1094 const struct i2c_target_callbacks *target_cb = data->target_cfg->callbacks; in target_i2c_isr()
1095 uint8_t *base = config->base; in target_i2c_isr()
1110 if (config->target_pio_mode) { in target_i2c_isr()
1115 data->target_nack = 1; in target_i2c_isr()
1120 target_cb->stop(data->target_cfg); in target_i2c_isr()
1122 if (data->target_nack) { in target_i2c_isr()
1126 data->target_nack = 0; in target_i2c_isr()
1143 struct i2c_enhance_data *data = dev->data; in i2c_enhance_isr()
1144 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_isr()
1147 if (data->target_attached) { in i2c_enhance_isr()
1152 uint8_t *base = config->base; in i2c_enhance_isr()
1166 irq_disable(config->i2c_irq_base); in i2c_enhance_isr()
1167 k_sem_give(&data->device_sync_sem); in i2c_enhance_isr()
1175 struct i2c_enhance_data *data = dev->data; in i2c_enhance_init()
1176 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_init()
1177 uint8_t *base = config->base; in i2c_enhance_init()
1178 uint8_t data_hold_time = config->data_hold_time; in i2c_enhance_init()
1183 if (!config->target_enable) { in i2c_enhance_init()
1186 k_mutex_init(&data->mutex); in i2c_enhance_init()
1187 k_sem_init(&data->device_sync_sem, 0, K_SEM_MAX_LIMIT); in i2c_enhance_init()
1191 (IT8XXX2_ECPM_BASE + (config->clock_gate_offset >> 8)); in i2c_enhance_init()
1192 uint8_t reg_mask = config->clock_gate_offset & 0xff; in i2c_enhance_init()
1195 /* Enable I2C function */ in i2c_enhance_init()
1199 /* reset i2c port */ in i2c_enhance_init()
1205 /* Set command address registers. */ in i2c_enhance_init()
1209 /* ChannelA-F switch selection of I2C pin */ in i2c_enhance_init()
1210 if (config->port == SMB_CHANNEL_A) { in i2c_enhance_init()
1212 config->channel_switch_sel; in i2c_enhance_init()
1213 } else if (config->port == SMB_CHANNEL_B) { in i2c_enhance_init()
1214 IT8XXX2_SMB_SMB01CHS = (config->channel_switch_sel << 4) | in i2c_enhance_init()
1216 } else if (config->port == SMB_CHANNEL_C) { in i2c_enhance_init()
1218 config->channel_switch_sel; in i2c_enhance_init()
1219 } else if (config->port == I2C_CHANNEL_D) { in i2c_enhance_init()
1220 IT8XXX2_SMB_SMB23CHS = (config->channel_switch_sel << 4) | in i2c_enhance_init()
1222 } else if (config->port == I2C_CHANNEL_E) { in i2c_enhance_init()
1224 config->channel_switch_sel; in i2c_enhance_init()
1225 } else if (config->port == I2C_CHANNEL_F) { in i2c_enhance_init()
1226 IT8XXX2_SMB_SMB45CHS = (config->channel_switch_sel << 4) | in i2c_enhance_init()
1230 /* Set I2C data hold time. */ in i2c_enhance_init()
1232 (data_hold_time - 3); in i2c_enhance_init()
1234 /* Set clock frequency for I2C ports */ in i2c_enhance_init()
1235 if (config->bitrate == I2C_BITRATE_STANDARD || in i2c_enhance_init()
1236 config->bitrate == I2C_BITRATE_FAST || in i2c_enhance_init()
1237 config->bitrate == I2C_BITRATE_FAST_PLUS) { in i2c_enhance_init()
1238 bitrate_cfg = i2c_map_dt_bitrate(config->bitrate); in i2c_enhance_init()
1245 data->i2ccs = I2C_CH_NORMAL; in i2c_enhance_init()
1248 LOG_ERR("i2c: failure initializing"); in i2c_enhance_init()
1255 /* Set the pin to I2C alternate function. */ in i2c_enhance_init()
1256 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in i2c_enhance_init()
1258 LOG_ERR("Failed to configure I2C pins"); in i2c_enhance_init()
1268 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_recover_bus()
1272 gpio_flags_t flags = GPIO_OUTPUT | (config->push_pull_recovery ? 0 : GPIO_OPEN_DRAIN); in i2c_enhance_recover_bus()
1273 /* Set SCL of I2C as GPIO pin */ in i2c_enhance_recover_bus()
1274 gpio_pin_configure_dt(&config->scl_gpios, flags); in i2c_enhance_recover_bus()
1275 /* Set SDA of I2C as GPIO pin */ in i2c_enhance_recover_bus()
1276 gpio_pin_configure_dt(&config->sda_gpios, flags); in i2c_enhance_recover_bus()
1279 * In I2C recovery bus, 1ms sleep interval for bitbanging i2c in i2c_enhance_recover_bus()
1284 gpio_pin_set_dt(&config->scl_gpios, 1); in i2c_enhance_recover_bus()
1285 gpio_pin_set_dt(&config->sda_gpios, 1); in i2c_enhance_recover_bus()
1289 gpio_pin_set_dt(&config->sda_gpios, 0); in i2c_enhance_recover_bus()
1291 gpio_pin_set_dt(&config->scl_gpios, 0); in i2c_enhance_recover_bus()
1297 gpio_pin_set_dt(&config->sda_gpios, 1); in i2c_enhance_recover_bus()
1299 gpio_pin_set_dt(&config->scl_gpios, 1); in i2c_enhance_recover_bus()
1302 gpio_pin_set_dt(&config->scl_gpios, 0); in i2c_enhance_recover_bus()
1306 gpio_pin_set_dt(&config->sda_gpios, 0); in i2c_enhance_recover_bus()
1310 gpio_pin_set_dt(&config->scl_gpios, 1); in i2c_enhance_recover_bus()
1312 gpio_pin_set_dt(&config->sda_gpios, 1); in i2c_enhance_recover_bus()
1315 /* Set GPIO back to I2C alternate function */ in i2c_enhance_recover_bus()
1316 status = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT); in i2c_enhance_recover_bus()
1318 LOG_ERR("Failed to configure I2C pins"); in i2c_enhance_recover_bus()
1322 /* reset i2c port */ in i2c_enhance_recover_bus()
1324 LOG_ERR("I2C ch%d reset cause %d", config->port, in i2c_enhance_recover_bus()
1334 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_target_register()
1335 struct i2c_enhance_data *data = dev->data; in i2c_enhance_target_register()
1336 uint8_t *base = config->base; in i2c_enhance_target_register()
1339 return -EINVAL; in i2c_enhance_target_register()
1342 if (target_cfg->flags & I2C_TARGET_FLAGS_ADDR_10_BITS) { in i2c_enhance_target_register()
1343 return -ENOTSUP; in i2c_enhance_target_register()
1346 if (data->target_attached) { in i2c_enhance_target_register()
1347 return -EBUSY; in i2c_enhance_target_register()
1350 data->target_cfg = target_cfg; in i2c_enhance_target_register()
1351 data->target_attached = true; in i2c_enhance_target_register()
1361 /* Peripheral address(8-bit) */ in i2c_enhance_target_register()
1362 IT8XXX2_I2C_IDR(base) = target_cfg->address << 1; in i2c_enhance_target_register()
1363 /* I2C interrupt enable and set acknowledge */ in i2c_enhance_target_register()
1369 /* I2C target initial configuration of PIO mode */ in i2c_enhance_target_register()
1370 if (config->target_pio_mode) { in i2c_enhance_target_register()
1374 /* I2C module enable */ in i2c_enhance_target_register()
1376 /* I2C target initial configuration of DMA mode */ in i2c_enhance_target_register()
1378 struct i2c_target_dma_buffer *target_buffer = &data->target_buffer; in i2c_enhance_target_register()
1383 memset(target_buffer->in_buffer, 0, buf_size); in i2c_enhance_target_register()
1384 memset(target_buffer->out_buffer, 0, buf_size); in i2c_enhance_target_register()
1386 in_data_addr = (uint32_t)target_buffer->in_buffer & 0xffffff; in i2c_enhance_target_register()
1387 out_data_addr = (uint32_t)target_buffer->out_buffer & 0xffffff; in i2c_enhance_target_register()
1419 /* I2C module enable and command queue mode */ in i2c_enhance_target_register()
1423 ite_intc_isr_clear(config->i2c_irq_base); in i2c_enhance_target_register()
1424 irq_enable(config->i2c_irq_base); in i2c_enhance_target_register()
1432 const struct i2c_enhance_config *config = dev->config; in i2c_enhance_target_unregister()
1433 struct i2c_enhance_data *data = dev->data; in i2c_enhance_target_unregister()
1435 if (!data->target_attached) { in i2c_enhance_target_unregister()
1436 return -EINVAL; in i2c_enhance_target_unregister()
1439 irq_disable(config->i2c_irq_base); in i2c_enhance_target_unregister()
1443 if (!config->target_pio_mode) { in i2c_enhance_target_unregister()
1447 data->target_cfg = NULL; in i2c_enhance_target_unregister()
1448 data->target_attached = false; in i2c_enhance_target_unregister()
1449 data->target_nack = 0; in i2c_enhance_target_unregister()
1455 static DEVICE_API(i2c, i2c_enhance_driver_api) = {
1471 "When I2C target config is enabled, the buffer mode must be used.");
1483 I2C_BITRATE_FAST_PLUS), "Not support I2C bit rate value"); \