Lines Matching refs:DEFINE_MM_REG_READ
168 DEFINE_MM_REG_READ(con, DW_IC_REG_CON, 32)
171 DEFINE_MM_REG_READ(cmd_data, DW_IC_REG_DATA_CMD, 32)
182 DEFINE_MM_REG_READ(intr_stat, DW_IC_REG_INTR_STAT, 32)
194 DEFINE_MM_REG_READ(clr_intr, DW_IC_REG_CLR_INTR, 32)
195 DEFINE_MM_REG_READ(clr_stop_det, DW_IC_REG_CLR_STOP_DET, 32)
196 DEFINE_MM_REG_READ(clr_start_det, DW_IC_REG_CLR_START_DET, 32)
197 DEFINE_MM_REG_READ(clr_gen_call, DW_IC_REG_CLR_GEN_CALL, 32)
198 DEFINE_MM_REG_READ(clr_tx_abrt, DW_IC_REG_CLR_TX_ABRT, 32)
199 DEFINE_MM_REG_READ(clr_rx_under, DW_IC_REG_CLR_RX_UNDER, 32)
200 DEFINE_MM_REG_READ(clr_rx_over, DW_IC_REG_CLR_RX_OVER, 32)
201 DEFINE_MM_REG_READ(clr_tx_over, DW_IC_REG_CLR_TX_OVER, 32)
202 DEFINE_MM_REG_READ(clr_rx_done, DW_IC_REG_CLR_RX_DONE, 32)
203 DEFINE_MM_REG_READ(clr_rd_req, DW_IC_REG_CLR_RD_REQ, 32)
204 DEFINE_MM_REG_READ(clr_activity, DW_IC_REG_CLR_ACTIVITY, 32)
217 DEFINE_MM_REG_READ(txflr, DW_IC_REG_TXFLR, 32)
218 DEFINE_MM_REG_READ(rxflr, DW_IC_REG_RXFLR, 32)
220 DEFINE_MM_REG_READ(dma_cr, DW_IC_REG_DMA_CR, 32)
223 DEFINE_MM_REG_READ(tdlr, DW_IC_REG_TDLR, 32)
225 DEFINE_MM_REG_READ(rdlr, DW_IC_REG_RDLR, 32)
228 DEFINE_MM_REG_READ(fs_spklen, DW_IC_REG_FS_SPKLEN, 32)
229 DEFINE_MM_REG_READ(hs_spklen, DW_IC_REG_HS_SPKLEN, 32)
231 DEFINE_MM_REG_READ(comp_param_1, DW_IC_REG_COMP_PARAM_1, 32)
232 DEFINE_MM_REG_READ(comp_type, DW_IC_REG_COMP_TYPE, 32)
233 DEFINE_MM_REG_READ(tar, DW_IC_REG_TAR, 32)