4  * SPDX-License-Identifier: Apache-2.0
27 	uint16_t addr, const uint8_t *data, uint32_t num, uint8_t flags);
29 	uint16_t addr, uint8_t *data, uint32_t num, uint8_t flags);
44 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_default_control()
47 	k_sem_init(&dev_data->bus_lock, 1, 1);  in i2c_atciic100_default_control()
48 	k_sem_init(&dev_data->device_sync_sem, 0, 1);  in i2c_atciic100_default_control()
60 		dev_data->fifo_depth = 2;  in i2c_atciic100_default_control()
63 		dev_data->fifo_depth = 4;  in i2c_atciic100_default_control()
66 		dev_data->fifo_depth = 8;  in i2c_atciic100_default_control()
69 		dev_data->fifo_depth = 16;  in i2c_atciic100_default_control()
74 	 * I2C setting: target mode(default), standard speed  in i2c_atciic100_default_control()
75 	 * 7-bit, CPU mode  in i2c_atciic100_default_control()
88 	dev_data->driver_state = I2C_DRV_INIT;  in i2c_atciic100_default_control()
89 	dev_data->status.mode = 0;  in i2c_atciic100_default_control()
90 	dev_data->status.arbitration_lost = 0;  in i2c_atciic100_default_control()
91 	dev_data->status.target_ack = 0;  in i2c_atciic100_default_control()
97 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_configure()
116 		ret = -EIO;  in i2c_atciic100_configure()
121 		ret = -EIO;  in i2c_atciic100_configure()
127 		dev_data->status.mode = 1;  in i2c_atciic100_configure()
130 		dev_data->status.mode = 0;  in i2c_atciic100_configure()
141 	dev_data->driver_state |= I2C_DRV_CFG_PARAM;  in i2c_atciic100_configure()
144 	k_sem_give(&dev_data->bus_lock);  in i2c_atciic100_configure()
150 	struct i2c_msg *msgs, uint8_t num_msgs, uint16_t addr)  in i2c_atciic100_transfer()  argument
152 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_transfer()
158 	k_sem_take(&dev_data->bus_lock, K_FOREVER);  in i2c_atciic100_transfer()
165 			return -EIO;  in i2c_atciic100_transfer()
172 					msgs[1].buf[count - msgs[0].len];  in i2c_atciic100_transfer()
175 		ret = i2c_atciic100_controller_send(dev, addr, burst_write_buf,  in i2c_atciic100_transfer()
183 				addr, msgs[i].buf, msgs[i].len, msgs[i].flags);  in i2c_atciic100_transfer()
186 				addr, msgs[i].buf, msgs[i].len, msgs[i].flags);  in i2c_atciic100_transfer()
196 	k_sem_give(&dev_data->bus_lock);  in i2c_atciic100_transfer()
202 	uint16_t addr, const uint8_t *data, uint32_t num, uint8_t flags)  in i2c_atciic100_controller_send()  argument
204 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_controller_send()
208 	 * Max to 10-bit address.  in i2c_atciic100_controller_send()
212 	if (addr > 0x3FF) {  in i2c_atciic100_controller_send()
213 		return -EIO;  in i2c_atciic100_controller_send()
221 	dev_data->status.mode = 1;  in i2c_atciic100_controller_send()
226 	/* Direction => tx:0, rx:1 */  in i2c_atciic100_controller_send()
227 	dev_data->status.arbitration_lost = 0;  in i2c_atciic100_controller_send()
228 	dev_data->status.target_ack = 0;  in i2c_atciic100_controller_send()
229 	dev_data->driver_state = I2C_DRV_CONTROLLER_TX;  in i2c_atciic100_controller_send()
241 	 * STOP condition triggered when transmission finish in controller mode.  in i2c_atciic100_controller_send()
243 	 * For 10-bit target address, we must set STOP bit.  in i2c_atciic100_controller_send()
263 	dev_data->target_addr = addr;  in i2c_atciic100_controller_send()
264 	dev_data->xfered_data_wt_ptr = 0;  in i2c_atciic100_controller_send()
265 	dev_data->xfer_wt_num = num;  in i2c_atciic100_controller_send()
266 	dev_data->middleware_tx_buf = (uint8_t *)data;  in i2c_atciic100_controller_send()
268 	/* In I2C target address, general call address = 0x0(7-bit or 10-bit) */  in i2c_atciic100_controller_send()
271 	reg |= (dev_data->target_addr & (TARGET_ADDR_MSK));  in i2c_atciic100_controller_send()
302 	k_sem_take(&dev_data->device_sync_sem, K_FOREVER);  in i2c_atciic100_controller_send()
304 	if (dev_data->status.target_ack != 1) {  in i2c_atciic100_controller_send()
305 		return -EIO;  in i2c_atciic100_controller_send()
307 	dev_data->status.target_ack = 0;  in i2c_atciic100_controller_send()
312 	uint16_t addr, uint8_t *data, uint32_t num, uint8_t flags)  in i2c_atciic100_controller_receive()  argument
314 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_controller_receive()
318 	 * Max to 10-bit address.  in i2c_atciic100_controller_receive()
322 	if (addr > 0x3FF) {  in i2c_atciic100_controller_receive()
323 		return -EIO;  in i2c_atciic100_controller_receive()
331 	dev_data->status.mode = 1;  in i2c_atciic100_controller_receive()
336 	/* Direction => tx:0, rx:1 */  in i2c_atciic100_controller_receive()
337 	dev_data->status.arbitration_lost = 0;  in i2c_atciic100_controller_receive()
338 	dev_data->status.target_ack = 0;  in i2c_atciic100_controller_receive()
339 	dev_data->driver_state = I2C_DRV_CONTROLLER_RX;  in i2c_atciic100_controller_receive()
351 	 * STOP condition triggered when transmission finish in Controller mode.  in i2c_atciic100_controller_receive()
353 	 * For 10-bit target address, we must set STOP bit.  in i2c_atciic100_controller_receive()
354 	 * I2C direction : controller rx, set xfer data count.  in i2c_atciic100_controller_receive()
371 	dev_data->target_addr = addr;  in i2c_atciic100_controller_receive()
372 	dev_data->xfered_data_rd_ptr = 0;  in i2c_atciic100_controller_receive()
373 	dev_data->xfer_rd_num = num;  in i2c_atciic100_controller_receive()
374 	dev_data->middleware_rx_buf = (uint8_t *)data;  in i2c_atciic100_controller_receive()
376 	/* In I2C target address, general call address = 0x0(7-bit or 10-bit) */  in i2c_atciic100_controller_receive()
379 	reg |= (dev_data->target_addr & (TARGET_ADDR_MSK));  in i2c_atciic100_controller_receive()
399 	k_sem_take(&dev_data->device_sync_sem, K_FOREVER);  in i2c_atciic100_controller_receive()
400 	if (dev_data->status.target_ack != 1) {  in i2c_atciic100_controller_receive()
401 		return -EIO;  in i2c_atciic100_controller_receive()
403 	dev_data->status.target_ack = 0;  in i2c_atciic100_controller_receive()
432 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_controller_fifo_write()
436 	write_fifo_count = dev_data->xfer_wt_num - dev_data->xfered_data_wt_ptr;  in i2c_controller_fifo_write()
438 	if (write_fifo_count >= dev_data->fifo_depth) {  in i2c_controller_fifo_write()
439 		write_fifo_count = dev_data->fifo_depth;  in i2c_controller_fifo_write()
450 			dev_data->middleware_tx_buf[dev_data->xfered_data_wt_ptr];  in i2c_controller_fifo_write()
452 		dev_data->xfered_data_wt_ptr++;  in i2c_controller_fifo_write()
455 		if (dev_data->xfered_data_wt_ptr == dev_data->xfer_wt_num) {  in i2c_controller_fifo_write()
466 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_controller_fifo_read()
470 	read_fifo_count = dev_data->xfer_rd_num - dev_data->xfered_data_rd_ptr;  in i2c_controller_fifo_read()
472 	if (read_fifo_count >= dev_data->fifo_depth) {  in i2c_controller_fifo_read()
473 		read_fifo_count = dev_data->fifo_depth;  in i2c_controller_fifo_read()
481 		dev_data->middleware_rx_buf[dev_data->xfered_data_rd_ptr] =  in i2c_controller_fifo_read()
483 		dev_data->xfered_data_rd_ptr++;  in i2c_controller_fifo_read()
486 		if (dev_data->xfered_data_rd_ptr == dev_data->xfer_rd_num) {  in i2c_controller_fifo_read()
496 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_fifo_empty_handler()
498 	if (dev_data->driver_state & I2C_DRV_CONTROLLER_TX) {  in i2c_fifo_empty_handler()
505 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_fifo_full_handler()
507 	if (dev_data->driver_state & I2C_DRV_CONTROLLER_RX) {  in i2c_fifo_full_handler()
514 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_cmpl_handler()
519 	/* Controller mode */  in i2c_cmpl_handler()
520 	if (dev_data->status.mode == 1) {  in i2c_cmpl_handler()
527 	if (dev_data->driver_state &  in i2c_cmpl_handler()
533 		if (dev_data->driver_state & I2C_DRV_CONTROLLER_TX) {  in i2c_cmpl_handler()
535 			dev_data->driver_state = I2C_DRV_CONTROLLER_TX_CMPL;  in i2c_cmpl_handler()
538 		if (dev_data->driver_state & I2C_DRV_CONTROLLER_RX) {  in i2c_cmpl_handler()
540 			/* Clear & set driver state to controller rx complete */  in i2c_cmpl_handler()
541 			dev_data->driver_state = I2C_DRV_CONTROLLER_RX_CMPL;  in i2c_cmpl_handler()
544 		k_sem_give(&dev_data->device_sync_sem);  in i2c_cmpl_handler()
548 	if (dev_data->driver_state & (I2C_DRV_TARGET_TX | I2C_DRV_TARGET_RX)) {  in i2c_cmpl_handler()
552 		if (dev_data->driver_state & I2C_DRV_TARGET_TX) {  in i2c_cmpl_handler()
553 			dev_data->driver_state = I2C_DRV_TARGET_TX_CMPL;  in i2c_cmpl_handler()
556 		if (dev_data->driver_state & I2C_DRV_TARGET_RX) {  in i2c_cmpl_handler()
557 			dev_data->driver_state = I2C_DRV_TARGET_RX_CMPL;  in i2c_cmpl_handler()
572 	/* Enable Byte Receive & Transfer for default target mode */  in i2c_cmpl_handler()
582 	reg |= (dev_data->target_config->address & (TARGET_ADDR_MSK));  in i2c_cmpl_handler()
585 	dev_data->driver_state = I2C_DRV_INIT;  in i2c_cmpl_handler()
586 	dev_data->status.mode = 0;  in i2c_cmpl_handler()
587 	dev_data->status.arbitration_lost = 0;  in i2c_cmpl_handler()
596 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in andes_i2c_target_event()
600 	 * Here is the entry for target mode driver to detect  in andes_i2c_target_event()
601 	 * target RX/TX action depend on controller TX/RX action.  in andes_i2c_target_event()
602 	 * A new I2C data transaction(START-ADDRESS-DATA-STOP)  in andes_i2c_target_event()
605 		if (k_sem_take(&dev_data->bus_lock, K_NO_WAIT) != 0) {  in andes_i2c_target_event()
610 			/* Notify middleware to do target rx action */  in andes_i2c_target_event()
611 			dev_data->driver_state = I2C_DRV_TARGET_TX;  in andes_i2c_target_event()
612 			dev_data->target_callbacks->read_requested  in andes_i2c_target_event()
613 				(dev_data->target_config, &val);  in andes_i2c_target_event()
618 			dev_data->driver_state = I2C_DRV_TARGET_RX;  in andes_i2c_target_event()
619 			dev_data->target_callbacks->write_requested  in andes_i2c_target_event()
620 				(dev_data->target_config);  in andes_i2c_target_event()
628 		dev_data->target_callbacks->write_received  in andes_i2c_target_event()
629 			(dev_data->target_config, val);  in andes_i2c_target_event()
641 		dev_data->target_callbacks->read_processed  in andes_i2c_target_event()
642 			(dev_data->target_config, &val);  in andes_i2c_target_event()
648 		k_sem_give(&dev_data->bus_lock);  in andes_i2c_target_event()
655 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_target_register()
660 	reg_addr |= (cfg->address & (TARGET_ADDR_MSK));  in i2c_atciic100_target_register()
664 	dev_data->target_callbacks = cfg->callbacks;  in i2c_atciic100_target_register()
665 	dev_data->target_config = cfg;  in i2c_atciic100_target_register()
668 	/* Enable Byte Receive & Transfer for default target mode */  in i2c_atciic100_target_register()
695 	struct i2c_atciic100_dev_data_t *dev_data = dev->data;  in i2c_atciic100_irq_handler()
707 	if (dev_data->status.mode == 0) {  in i2c_atciic100_irq_handler()
713 		dev_data->status.target_ack = 1;  in i2c_atciic100_irq_handler()
731 		dev_data->status.arbitration_lost = 1;  in i2c_atciic100_irq_handler()
749 	const struct i2c_atciic100_config *dev_cfg = dev->config;  in i2c_atciic100_init()
756 	dev_cfg->dt_init_fn();  in i2c_atciic100_init()
766 	irq_enable(dev_cfg->irq_num);  in i2c_atciic100_init()