Lines Matching +full:interrupt +full:- +full:direction
6 * SPDX-License-Identifier: Apache-2.0
24 #define DEV_CFG(_dev) ((const struct gpio_xlnx_ps_bank_dev_cfg *)(_dev)->config)
25 #define DEV_DATA(_dev) ((struct gpio_xlnx_ps_bank_dev_data *const)(_dev)->data)
34 * - Pull up
35 * - Pull down
36 * - Open drain
37 * - Open source.
45 * -EINVAL if the specified pin index is out of range,
46 * -ENOTSUP if the pin configuration data contains a flag
64 return -ENOTSUP; in gpio_xlnx_ps_pin_configure()
67 /* Read the data direction & output enable registers */ in gpio_xlnx_ps_pin_configure()
77 * direction register to be written *BEFORE* the data in gpio_xlnx_ps_pin_configure()
88 * -> Write the initial output value into the data register. in gpio_xlnx_ps_pin_configure()
105 * Disable the output first in case of an O -> I in gpio_xlnx_ps_pin_configure()
106 * transition, then change the pin's direction. in gpio_xlnx_ps_pin_configure()
119 * read-only data register. This includes the current values
129 * -EINVAL if the pointer to the output variable is NULL.
182 * as a read-modify-write operation. All bits set in the bit
211 * as a read-modify-write operation. All bits set in the bit
240 * as a read-modify-write operation. All bits set in the bit
266 * @brief Configures the interrupt behaviour of a pin within the
269 * Configures the interrupt behaviour of a pin within the current
270 * GPIO bank. If a pin is to be configured to trigger an interrupt,
273 * - edge or level triggered,
274 * - rising edge / high level or falling edge / low level,
275 * - in edge mode only: trigger on both rising and falling edge.
280 * @param mode Mode configuration: edge, level or interrupt disabled.
284 * @retval 0 if the interrupt configuration completed successfully,
285 * -EINVAL if the specified pin index is out of range,
286 * -ENOTSUP if the interrupt configuration data contains an
303 /* Disable the specified pin's interrupt before (re-)configuring it */ in gpio_xlnx_ps_bank_pin_irq_configure()
317 return -EINVAL; in gpio_xlnx_ps_bank_pin_irq_configure()
328 return -EINVAL; in gpio_xlnx_ps_bank_pin_irq_configure()
344 /* Clear potential stale pending bit before enabling interrupt */ in gpio_xlnx_ps_bank_pin_irq_configure()
353 * @brief Returns the interrupt status of the current GPIO bank.
355 * Returns the interrupt status of the current GPIO bank, in the
356 * form of a bit mask where each pin with a pending interrupt is
357 * indicated. This information can either be used by the PM sub-
359 * the interrupt line of the entire PS GPIO controller, regardless
360 * of how many bank sub-devices exist. As the current status is
367 * an interrupt is pending.
384 * @brief Callback management re-direction function.
386 * Re-directs any callback management calls relating to the current
387 * GPIO bank to the GPIO sub-system. Comp. documentation of the
388 * underlying sub-system's #gpio_manage_callback function.
395 * an interrupt is pending.
403 return gpio_manage_callback(&dev_data->callbacks, callback, set); in gpio_xlnx_ps_bank_manage_callback()
420 * @brief Initialize a MIO / EMIO GPIO bank sub-device
422 * Initialize a MIO / EMIO GPIO bank sub-device, which is a child
423 * of the parent Xilinx PS GPIO controller device driver. This ini-
436 __ASSERT(dev_data->base != 0, "%s mapped base address missing", dev->name); in gpio_xlnx_ps_bank_init()
437 if (dev_data->base == 0) { in gpio_xlnx_ps_bank_init()
438 LOG_ERR("%s mapped base address missing", dev->name); in gpio_xlnx_ps_bank_init()
439 return -EIO; in gpio_xlnx_ps_bank_init()