Lines Matching refs:base
39 mm_reg_t base; member
69 return sys_read32(config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_read_data()
76 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_DATA_OFFSET); in gpio_xlnx_axi_write_data()
83 sys_write32(val, config->base + (config->channel * GPIO2_OFFSET) + GPIO_TRI_OFFSET); in gpio_xlnx_axi_write_tri()
243 enabled_interrupts = sys_read32(config->base + IPIER_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()
249 if (sys_read32(config->base + IPISR_OFFSET) & chan_mask) { in gpio_xlnx_axi_pin_interrupt_configure()
250 sys_write32(chan_mask, config->base + IPISR_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()
259 sys_write32(enabled_interrupts, config->base + IPIER_OFFSET); in gpio_xlnx_axi_pin_interrupt_configure()
297 interrupt_flags = sys_read32(config->base + IPISR_OFFSET); in gpio_xlnx_axi_get_pending_int()
305 sys_write32(chan_mask, config->base + IPISR_OFFSET); in gpio_xlnx_axi_get_pending_int()
355 sys_write32(0x0, config->base + IPIER_OFFSET); in gpio_xlnx_axi_init()
358 sys_write32(sys_read32(config->base + IPISR_OFFSET), config->base + IPISR_OFFSET); in gpio_xlnx_axi_init()
361 sys_write32(GIER_GIE, config->base + GIER_OFFSET); in gpio_xlnx_axi_init()
404 .base = DT_INST_REG_ADDR(n), \
434 .base = DT_INST_REG_ADDR(n), \