Lines Matching +full:int +full:- +full:pin
2 * Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
4 * SPDX-License-Identifier: Apache-2.0
26 /* sifive GPIO register-set structure */
28 unsigned int in_val;
29 unsigned int in_en;
30 unsigned int out_en;
31 unsigned int out_val;
32 unsigned int pue;
33 unsigned int ds;
34 unsigned int rise_ie;
35 unsigned int rise_ip;
36 unsigned int fall_ie;
37 unsigned int fall_ip;
38 unsigned int high_ie;
39 unsigned int high_ip;
40 unsigned int low_ie;
41 unsigned int low_ip;
42 unsigned int iof_en;
43 unsigned int iof_sel;
44 unsigned int invert;
51 /* multi-level encoded interrupt corresponding to pin 0 */
65 ((const struct gpio_sifive_config * const)(dev)->config)
67 ((volatile struct gpio_sifive_t *)(DEV_GPIO_CFG(dev))->gpio_base_addr)
69 ((struct gpio_sifive_data *)(dev)->data)
72 /* Given gpio_irq_base and the pin number, return the IRQ number for the pin */
73 static inline unsigned int gpio_sifive_pin_irq(unsigned int base_irq, int pin) in gpio_sifive_pin_irq() argument
75 unsigned int level = irq_get_level(base_irq); in gpio_sifive_pin_irq()
76 unsigned int pin_irq = 0; in gpio_sifive_pin_irq()
79 pin_irq = base_irq + pin; in gpio_sifive_pin_irq()
81 pin_irq = base_irq + (pin << CONFIG_1ST_LEVEL_INTERRUPT_BITS); in gpio_sifive_pin_irq()
87 /* Given the PLIC source number, return the number of the GPIO pin associated
90 static inline int gpio_sifive_plic_to_pin(unsigned int base_irq, int plic_irq) in gpio_sifive_plic_to_pin()
92 unsigned int level = irq_get_level(base_irq); in gpio_sifive_plic_to_pin()
98 return (plic_irq - base_irq); in gpio_sifive_plic_to_pin()
107 /* Calculate pin and mask from base level 2 line */ in gpio_sifive_irq_handler()
108 uint8_t pin = 1 + (riscv_plic_get_irq() - in gpio_sifive_irq_handler() local
109 (uint8_t)(cfg->gpio_irq_base >> CONFIG_1ST_LEVEL_INTERRUPT_BITS)); in gpio_sifive_irq_handler()
116 * It is certainly possible, especially on double-edge, that in gpio_sifive_irq_handler()
124 gpio->rise_ip = BIT(pin); in gpio_sifive_irq_handler()
125 gpio->fall_ip = BIT(pin); in gpio_sifive_irq_handler()
126 gpio->high_ip = BIT(pin); in gpio_sifive_irq_handler()
127 gpio->low_ip = BIT(pin); in gpio_sifive_irq_handler()
129 /* Call the corresponding callback registered for the pin */ in gpio_sifive_irq_handler()
130 gpio_fire_callbacks(&data->cb, dev, BIT(pin)); in gpio_sifive_irq_handler()
134 * @brief Configure pin
137 * @param pin The pin number
138 * @param flags Flags of pin or port
142 static int gpio_sifive_config(const struct device *dev, in gpio_sifive_config()
143 gpio_pin_t pin, in gpio_sifive_config() argument
148 /* We cannot support open-source open-drain configuration */ in gpio_sifive_config()
150 return -ENOTSUP; in gpio_sifive_config()
153 /* We only support pull-ups, not pull-downs */ in gpio_sifive_config()
155 return -ENOTSUP; in gpio_sifive_config()
158 /* Set pull-up if requested */ in gpio_sifive_config()
159 WRITE_BIT(gpio->pue, pin, flags & GPIO_PULL_UP); in gpio_sifive_config()
165 gpio->out_val |= BIT(pin); in gpio_sifive_config()
168 gpio->out_val &= ~BIT(pin); in gpio_sifive_config()
172 WRITE_BIT(gpio->out_en, pin, flags & GPIO_OUTPUT); in gpio_sifive_config()
173 WRITE_BIT(gpio->in_en, pin, flags & GPIO_INPUT); in gpio_sifive_config()
178 static int gpio_sifive_port_get_raw(const struct device *dev, in gpio_sifive_port_get_raw()
183 *value = gpio->in_val; in gpio_sifive_port_get_raw()
188 static int gpio_sifive_port_set_masked_raw(const struct device *dev, in gpio_sifive_port_set_masked_raw()
194 gpio->out_val = (gpio->out_val & ~mask) | (value & mask); in gpio_sifive_port_set_masked_raw()
199 static int gpio_sifive_port_set_bits_raw(const struct device *dev, in gpio_sifive_port_set_bits_raw()
204 gpio->out_val |= mask; in gpio_sifive_port_set_bits_raw()
209 static int gpio_sifive_port_clear_bits_raw(const struct device *dev, in gpio_sifive_port_clear_bits_raw()
214 gpio->out_val &= ~mask; in gpio_sifive_port_clear_bits_raw()
219 static int gpio_sifive_port_toggle_bits(const struct device *dev, in gpio_sifive_port_toggle_bits()
224 gpio->out_val ^= mask; in gpio_sifive_port_toggle_bits()
229 static int gpio_sifive_pin_interrupt_configure(const struct device *dev, in gpio_sifive_pin_interrupt_configure()
230 gpio_pin_t pin, in gpio_sifive_pin_interrupt_configure() argument
237 gpio->rise_ie &= ~BIT(pin); in gpio_sifive_pin_interrupt_configure()
238 gpio->fall_ie &= ~BIT(pin); in gpio_sifive_pin_interrupt_configure()
239 gpio->high_ie &= ~BIT(pin); in gpio_sifive_pin_interrupt_configure()
240 gpio->low_ie &= ~BIT(pin); in gpio_sifive_pin_interrupt_configure()
244 irq_disable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin)); in gpio_sifive_pin_interrupt_configure()
249 gpio->high_ip = BIT(pin); in gpio_sifive_pin_interrupt_configure()
250 gpio->high_ie |= BIT(pin); in gpio_sifive_pin_interrupt_configure()
253 gpio->low_ip = BIT(pin); in gpio_sifive_pin_interrupt_configure()
254 gpio->low_ie |= BIT(pin); in gpio_sifive_pin_interrupt_configure()
256 irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin)); in gpio_sifive_pin_interrupt_configure()
263 gpio->rise_ip = BIT(pin); in gpio_sifive_pin_interrupt_configure()
264 gpio->rise_ie |= BIT(pin); in gpio_sifive_pin_interrupt_configure()
267 gpio->fall_ip = BIT(pin); in gpio_sifive_pin_interrupt_configure()
268 gpio->fall_ie |= BIT(pin); in gpio_sifive_pin_interrupt_configure()
270 irq_enable(gpio_sifive_pin_irq(cfg->gpio_irq_base, pin)); in gpio_sifive_pin_interrupt_configure()
274 return -ENOTSUP; in gpio_sifive_pin_interrupt_configure()
280 static int gpio_sifive_manage_callback(const struct device *dev, in gpio_sifive_manage_callback()
286 return gpio_manage_callback(&data->cb, callback, set); in gpio_sifive_manage_callback()
290 static int gpio_sifive_port_get_dir(const struct device *dev, gpio_port_pins_t map, in gpio_sifive_port_get_dir()
295 map &= cfg->common.port_pin_mask; in gpio_sifive_port_get_dir()
298 *inputs = map & DEV_GPIO(dev)->in_en; in gpio_sifive_port_get_dir()
302 *outputs = map & DEV_GPIO(dev)->out_en; in gpio_sifive_port_get_dir()
332 static int gpio_sifive_init(const struct device *dev) in gpio_sifive_init()
338 gpio->in_en = 0U; in gpio_sifive_init()
339 gpio->out_en = 0U; in gpio_sifive_init()
340 gpio->pue = 0U; in gpio_sifive_init()
341 gpio->rise_ie = 0U; in gpio_sifive_init()
342 gpio->fall_ie = 0U; in gpio_sifive_init()
343 gpio->high_ie = 0U; in gpio_sifive_init()
344 gpio->low_ie = 0U; in gpio_sifive_init()
345 gpio->iof_en = 0U; in gpio_sifive_init()
346 gpio->iof_sel = 0U; in gpio_sifive_init()
347 gpio->invert = 0U; in gpio_sifive_init()
349 /* Setup IRQ handler for each gpio pin */ in gpio_sifive_init()
350 cfg->gpio_cfg_func(); in gpio_sifive_init()