3  * Copyright (c) 2020-2023 Gerson Fernando Budke <nandojve@gmail.com>
5  * SPDX-License-Identifier: Apache-2.0
15 #include <zephyr/drivers/gpio.h>
19 #include <zephyr/drivers/gpio/gpio_utils.h>
26 	Gpio *regs;
44 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_configure()
45 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_configure()  local
49 		return -ENOTSUP;  in gpio_sam_port_configure()
53 		gpio->IERC = mask;  in gpio_sam_port_configure()
54 		gpio->PUERC = mask;  in gpio_sam_port_configure()
55 		gpio->PDERC = mask;  in gpio_sam_port_configure()
56 		gpio->GPERS = mask;  in gpio_sam_port_configure()
57 		gpio->ODERC = mask;  in gpio_sam_port_configure()
58 		gpio->STERC = mask;  in gpio_sam_port_configure()
64 	 * Always enable schmitt-trigger because SAM4L GPIO Ctrl  in gpio_sam_port_configure()
67 	gpio->STERS = mask;  in gpio_sam_port_configure()
71 			gpio->OVRS = mask;  in gpio_sam_port_configure()
74 			gpio->OVRC = mask;  in gpio_sam_port_configure()
76 		gpio->ODERS = mask;  in gpio_sam_port_configure()
78 		gpio->ODERC = mask;  in gpio_sam_port_configure()
81 	gpio->PUERC = mask;  in gpio_sam_port_configure()
82 	gpio->PDERC = mask;  in gpio_sam_port_configure()
84 		gpio->PUERS = mask;  in gpio_sam_port_configure()
86 		gpio->PDERS = mask;  in gpio_sam_port_configure()
89 	/* Enable the GPIO to control the pin (instead of a peripheral). */  in gpio_sam_port_configure()
90 	gpio->GPERS = mask;  in gpio_sam_port_configure()
105 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_get_raw()
106 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_get_raw()  local
108 	*value = gpio->PVR;  in gpio_sam_port_get_raw()
117 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_set_masked_raw()
118 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_set_masked_raw()  local
120 	gpio->OVR = (gpio->PVR & ~mask) | (mask & value);  in gpio_sam_port_set_masked_raw()
128 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_set_bits_raw()
129 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_set_bits_raw()  local
131 	gpio->OVRS = mask;  in gpio_sam_port_set_bits_raw()
139 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_clear_bits_raw()
140 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_clear_bits_raw()  local
142 	gpio->OVRC = mask;  in gpio_sam_port_clear_bits_raw()
150 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_toggle_bits()
151 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_toggle_bits()  local
153 	gpio->OVRT = mask;  in gpio_sam_port_toggle_bits()
163 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_port_interrupt_configure()
164 	Gpio * const gpio = cfg->regs;  in gpio_sam_port_interrupt_configure()  local
167 		return -ENOTSUP;  in gpio_sam_port_interrupt_configure()
170 	gpio->IERC = mask;  in gpio_sam_port_interrupt_configure()
171 	gpio->IMR0C = mask;  in gpio_sam_port_interrupt_configure()
172 	gpio->IMR1C = mask;  in gpio_sam_port_interrupt_configure()
176 			gpio->IMR0S = mask;  in gpio_sam_port_interrupt_configure()
178 			gpio->IMR1S = mask;  in gpio_sam_port_interrupt_configure()
183 		gpio->IFRC = mask;  in gpio_sam_port_interrupt_configure()
184 		gpio->IERS = mask;  in gpio_sam_port_interrupt_configure()
200 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_isr()
201 	Gpio * const gpio = cfg->regs;  in gpio_sam_isr()  local
202 	struct gpio_sam_runtime *context = dev->data;  in gpio_sam_isr()
205 	int_stat = gpio->IFR;  in gpio_sam_isr()
206 	gpio->IFRC = int_stat;  in gpio_sam_isr()
208 	gpio_fire_callbacks(&context->cb, dev, int_stat);  in gpio_sam_isr()
215 	struct gpio_sam_runtime *context = port->data;  in gpio_sam_manage_callback()
217 	return gpio_manage_callback(&context->cb, callback, set);  in gpio_sam_manage_callback()
220 static DEVICE_API(gpio, gpio_sam_api) = {
233 	const struct gpio_sam_config * const cfg = dev->config;  in gpio_sam_init()
235 	/* Enable GPIO clock in PM */  in gpio_sam_init()
237 			       (clock_control_subsys_t)&cfg->clock_cfg);  in gpio_sam_init()
239 	cfg->config_func(dev);  in gpio_sam_init()
244 #define GPIO_SAM_IRQ_CONNECT(n, m)					\  argument
246 		IRQ_CONNECT(DT_INST_IRQ_BY_IDX(n, m, irq),		\
247 			    DT_INST_IRQ_BY_IDX(n, m, priority),		\
249 			    DEVICE_DT_INST_GET(n), 0);			\
250 		irq_enable(DT_INST_IRQ_BY_IDX(n, m, irq));		\
253 #define GPIO_SAM_INIT(n)						\  argument
254 	static void port_##n##_sam_config_func(const struct device *dev);\
256 	static const struct gpio_sam_config port_##n##_sam_config = {	\
258 			.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(n),\
260 		.regs = (Gpio *)DT_INST_REG_ADDR(n),			\
261 		.clock_cfg = SAM_DT_INST_CLOCK_PMC_CFG(n),		\
262 		.config_func = port_##n##_sam_config_func,		\
265 	static struct gpio_sam_runtime port_##n##_sam_runtime;		\
267 	DEVICE_DT_INST_DEFINE(n, gpio_sam_init, NULL,			\
268 			    &port_##n##_sam_runtime,			\
269 			    &port_##n##_sam_config, PRE_KERNEL_1,	\
273 	static void port_##n##_sam_config_func(const struct device *dev)\
275 		GPIO_SAM_IRQ_CONNECT(n, 0);				\
276 		GPIO_SAM_IRQ_CONNECT(n, 1);				\
277 		GPIO_SAM_IRQ_CONNECT(n, 2);				\
278 		GPIO_SAM_IRQ_CONNECT(n, 3);				\