4  * SPDX-License-Identifier: Apache-2.0
20 #define LOG_DEV_ERR(dev, format, ...) LOG_ERR("%s:" #format, (dev)->name, ##__VA_ARGS__)
21 #define LOG_DEV_DBG(dev, format, ...) LOG_DBG("%s:" #format, (dev)->name, ##__VA_ARGS__)
60 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_pin_get_config()
61 	bsp_io_port_pin_t port_pin = config->fsp_port | pin;  in gpio_rz_pin_get_config()
100 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_pin_configure()
101 	struct gpio_rz_data *data = dev->data;  in gpio_rz_pin_configure()
102 	bsp_io_port_pin_t port_pin = config->fsp_port | pin;  in gpio_rz_pin_configure()
152 		/* Filter register, see in renesas-rz-gpio-ioport.h */  in gpio_rz_pin_configure()
155 		return -ENOTSUP;  in gpio_rz_pin_configure()
158 	err = config->fsp_api->pinCfg(data->fsp_ctrl, port_pin, ioport_config_data);  in gpio_rz_pin_configure()
160 		return -EIO;  in gpio_rz_pin_configure()
167 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_port_get_raw()
168 	struct gpio_rz_data *data = dev->data;  in gpio_rz_port_get_raw()
172 	err = config->fsp_api->portRead(data->fsp_ctrl, config->fsp_port, &port_value);  in gpio_rz_port_get_raw()
174 		return -EIO;  in gpio_rz_port_get_raw()
183 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_port_set_masked_raw()
184 	struct gpio_rz_data *data = dev->data;  in gpio_rz_port_set_masked_raw()
189 	err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, port_value, port_mask);  in gpio_rz_port_set_masked_raw()
191 		return -EIO;  in gpio_rz_port_set_masked_raw()
198 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_port_set_bits_raw()
199 	struct gpio_rz_data *data = dev->data;  in gpio_rz_port_set_bits_raw()
204 	err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask);  in gpio_rz_port_set_bits_raw()
206 		return -EIO;  in gpio_rz_port_set_bits_raw()
213 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_port_clear_bits_raw()
214 	struct gpio_rz_data *data = dev->data;  in gpio_rz_port_clear_bits_raw()
219 	err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value, mask);  in gpio_rz_port_clear_bits_raw()
221 		return -EIO;  in gpio_rz_port_clear_bits_raw()
228 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_port_toggle_bits()
229 	struct gpio_rz_data *data = dev->data;  in gpio_rz_port_toggle_bits()
235 	for (uint8_t idx = 0; idx < config->ngpios; idx++) {  in gpio_rz_port_toggle_bits()
237 			port_pin = config->fsp_port | idx;  in gpio_rz_port_toggle_bits()
246 	err = config->fsp_api->portWrite(data->fsp_ctrl, config->fsp_port, value,  in gpio_rz_port_toggle_bits()
249 		return -EIO;  in gpio_rz_port_toggle_bits()
259 	struct gpio_rz_tint_data *data = dev->data;  in gpio_rz_int_disable()
260 	volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;  in gpio_rz_int_disable()
261 	volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;  in gpio_rz_int_disable()
262 	volatile uint32_t *tscr = &R_INTC_IM33->TSCR;  in gpio_rz_int_disable()
275 	if (data->irq_set_edge & BIT(tint_num)) {  in gpio_rz_int_disable()
277 		data->irq_set_edge &= ~BIT(tint_num);  in gpio_rz_int_disable()
279 	data->tint_data[tint_num].gpio_dev = NULL;  in gpio_rz_int_disable()
280 	data->tint_data[tint_num].pin = UINT8_MAX;  in gpio_rz_int_disable()
288 	struct gpio_rz_tint_data *int_data = int_dev->data;  in gpio_rz_int_enable()
289 	const struct gpio_rz_config *gpio_config = gpio_dev->config;  in gpio_rz_int_enable()  local
290 	volatile uint32_t *tssr = &R_INTC_IM33->TSSR0;  in gpio_rz_int_enable()
291 	volatile uint32_t *titsr = &R_INTC_IM33->TITSR0;  in gpio_rz_int_enable()
298 	*tssr |= (GPIO_RZ_TSSR_VAL(gpio_config->port_num, pin)) << GPIO_RZ_TSSR_OFFSET(tint_num);  in gpio_rz_int_enable()
301 		int_data->irq_set_edge |= BIT(tint_num);  in gpio_rz_int_enable()
303 		R_INTC_IM33->TSCR &= ~BIT(tint_num);  in gpio_rz_int_enable()
305 	int_data->tint_data[tint_num].gpio_dev = gpio_dev;  in gpio_rz_int_enable()
306 	int_data->tint_data[tint_num].pin = pin;  in gpio_rz_int_enable()
315 	const struct gpio_rz_config *config = dev->config;  in gpio_rz_pin_interrupt_configure()
316 	struct gpio_rz_data *data = dev->data;  in gpio_rz_pin_interrupt_configure()
317 	bsp_io_port_pin_t port_pin = config->fsp_port | pin;  in gpio_rz_pin_interrupt_configure()
318 	uint8_t tint_num = config->tint_num[pin];  in gpio_rz_pin_interrupt_configure()
327 	if (pin > config->ngpios) {  in gpio_rz_pin_interrupt_configure()
328 		return -EINVAL;  in gpio_rz_pin_interrupt_configure()
332 		return -ENOTSUP;  in gpio_rz_pin_interrupt_configure()
335 	key = k_spin_lock(&data->lock);  in gpio_rz_pin_interrupt_configure()
341 		gpio_rz_int_disable(config->int_dev, tint_num);  in gpio_rz_pin_interrupt_configure()
361 	gpio_rz_int_enable(config->int_dev, dev, tint_num, irq_type, pin);  in gpio_rz_pin_interrupt_configure()
364 	k_spin_unlock(&data->lock, key);  in gpio_rz_pin_interrupt_configure()
371 	struct gpio_rz_data *data = dev->data;  in gpio_rz_manage_callback()
373 	return gpio_manage_callback(&data->cb, callback, set);  in gpio_rz_manage_callback()
378 	struct gpio_rz_data *data = dev->data;  in gpio_rz_isr()
380 	gpio_fire_callbacks(&data->cb, dev, BIT(pin));  in gpio_rz_isr()
385 	struct gpio_rz_tint_data *data = dev->data;  in gpio_rz_tint_isr()
386 	volatile uint32_t *tscr = &R_INTC_IM33->TSCR;  in gpio_rz_tint_isr()
389 	tint_num = irq - GPIO_RZ_TINT_IRQ_OFFSET;  in gpio_rz_tint_isr()
396 	if (data->irq_set_edge & BIT(tint_num)) {  in gpio_rz_tint_isr()
400 	gpio_rz_isr(data->tint_data[tint_num].gpio_dev, data->tint_data[tint_num].pin);  in gpio_rz_tint_isr()
405 	const struct gpio_rz_tint_config *config = dev->config;  in gpio_rz_int_init()
407 	config->gpio_int_init();  in gpio_rz_int_init()