2  * Copyright 2022-2024 NXP
4  * SPDX-License-Identifier: Apache-2.0
10 #include <zephyr/drivers/gpio.h>
11 #include <zephyr/drivers/gpio/gpio_utils.h>
13 #include <zephyr/dt-bindings/gpio/nxp-s32-gpio.h>
26 #define SIUL2_MSCR(n) (0x4 * (n))  argument
27 /* SIUL2 Parallel GPIO Pad Data Out (offset from gpio base) */
29 /* SIUL2 Parallel GPIO Pad Data In */
33 #define GPIO_READ(r)      sys_read16(config->gpio_base + (r))
34 #define GPIO_WRITE(r, v)  sys_write16((v), config->gpio_base + (r))
35 #define PORT_READ(p)      sys_read32(config->port_base + SIUL2_MSCR(p))
36 #define PORT_WRITE(p, v)  sys_write32((v), config->port_base + SIUL2_MSCR(p))
86 	const struct gpio_nxp_s32_config *config = dev->config;  in nxp_s32_gpio_configure()
91 		return -ENOTSUP;  in nxp_s32_gpio_configure()
95 	struct gpio_nxp_s32_data *data = dev->data;  in nxp_s32_gpio_configure()
97 	WRITE_BIT(data->pin_wkpu_mask, pin, (flags & NXP_S32_GPIO_INT_WKPU));  in nxp_s32_gpio_configure()
100 		return -ENOTSUP;  in nxp_s32_gpio_configure()
113 			pgpdo_val |= BIT(15 - pin);  in nxp_s32_gpio_configure()
115 			pgpdo_val &= ~BIT(15 - pin);  in nxp_s32_gpio_configure()
135 	const struct gpio_nxp_s32_config *config = port->config;  in nxp_s32_gpio_port_get_raw()
146 	const struct gpio_nxp_s32_config *config = port->config;  in nxp_s32_gpio_port_set_masked_raw()
159 	const struct gpio_nxp_s32_config *config = port->config;  in nxp_s32_gpio_port_set_bits_raw()
172 	const struct gpio_nxp_s32_config *config = port->config;  in nxp_s32_gpio_port_clear_bits_raw()
185 	const struct gpio_nxp_s32_config *config = port->config;  in nxp_s32_gpio_port_toggle_bits()
202 	for (i = 0; i < irq_cfg->map_cnt; i++) {  in nxp_s32_gpio_pin_to_line()
203 		if (irq_cfg->map[i].pin == pin) {  in nxp_s32_gpio_pin_to_line()
204 			return irq_cfg->map[i].line;  in nxp_s32_gpio_pin_to_line()
214 	struct gpio_nxp_s32_data *data = dev->data;  in nxp_s32_gpio_isr()
216 	gpio_fire_callbacks(&data->callbacks, dev, BIT(pin));  in nxp_s32_gpio_isr()
234 		return -ENOTSUP;  in nxp_s32_gpio_eirq_get_trigger()
245 	const struct gpio_nxp_s32_config *config = dev->config;  in nxp_s32_gpio_config_eirq()
246 	const struct gpio_nxp_s32_irq_config *irq_cfg = config->eirq_info;  in nxp_s32_gpio_config_eirq()
252 		return -ENOTSUP;  in nxp_s32_gpio_config_eirq()
256 		return -ENOTSUP;  in nxp_s32_gpio_config_eirq()
265 		return -ENOTSUP;  in nxp_s32_gpio_config_eirq()
269 		eirq_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line);  in nxp_s32_gpio_config_eirq()
270 		eirq_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line);  in nxp_s32_gpio_config_eirq()
273 			return -ENOTSUP;  in nxp_s32_gpio_config_eirq()
275 		if (eirq_nxp_s32_set_callback(irq_cfg->ctrl, irq_line, pin,  in nxp_s32_gpio_config_eirq()
278 			return -EBUSY;  in nxp_s32_gpio_config_eirq()
280 		eirq_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, eirq_trigger);  in nxp_s32_gpio_config_eirq()
302 		return -ENOTSUP;  in nxp_s32_gpio_wkpu_get_trigger()
313 	const struct gpio_nxp_s32_config *config = dev->config;  in nxp_s32_gpio_config_wkpu()
314 	const struct gpio_nxp_s32_irq_config *irq_cfg = config->wkpu_info;  in nxp_s32_gpio_config_wkpu()
320 		return -ENOTSUP;  in nxp_s32_gpio_config_wkpu()
324 		return -ENOTSUP;  in nxp_s32_gpio_config_wkpu()
333 		return -ENOTSUP;  in nxp_s32_gpio_config_wkpu()
337 		wkpu_nxp_s32_disable_interrupt(irq_cfg->ctrl, irq_line);  in nxp_s32_gpio_config_wkpu()
338 		wkpu_nxp_s32_unset_callback(irq_cfg->ctrl, irq_line);  in nxp_s32_gpio_config_wkpu()
341 			return -ENOTSUP;  in nxp_s32_gpio_config_wkpu()
343 		if (wkpu_nxp_s32_set_callback(irq_cfg->ctrl, irq_line, pin,  in nxp_s32_gpio_config_wkpu()
346 			return -EBUSY;  in nxp_s32_gpio_config_wkpu()
348 		wkpu_nxp_s32_enable_interrupt(irq_cfg->ctrl, irq_line, wkpu_trigger);  in nxp_s32_gpio_config_wkpu()
361 	struct gpio_nxp_s32_data *data = dev->data;  in nxp_s32_gpio_pin_interrupt_configure()
363 	if (data->pin_wkpu_mask & BIT(pin)) {  in nxp_s32_gpio_pin_interrupt_configure()
376 	struct gpio_nxp_s32_data *data = dev->data;  in nxp_s32_gpio_manage_callback()
378 	return gpio_manage_callback(&data->callbacks, cb, set);  in nxp_s32_gpio_manage_callback()
387 	const struct gpio_nxp_s32_config *config = dev->config;  in nxp_s32_gpio_pin_get_config()
401 		if ((pins_output & BIT(15 - pin)) != 0) {  in nxp_s32_gpio_pin_get_config()
434 	const struct gpio_nxp_s32_config *config = dev->config;  in nxp_s32_gpio_port_get_direction()
439 	map &= config->common.port_pin_mask;  in nxp_s32_gpio_port_get_direction()
443 			pin = find_lsb_set(map) - 1;  in nxp_s32_gpio_port_get_direction()
453 			pin = find_lsb_set(map) - 1;  in nxp_s32_gpio_port_get_direction()
465 static DEVICE_API(gpio, gpio_nxp_s32_driver_api) = {
484 /* Calculate the port pin mask based on ngpios and gpio-reserved-ranges node
487  * For example, for the following gpio node definition:
489  *	gpioo: gpio@40521716 {
492  *		gpio-reserved-ranges = <0 10>;
497 #define GPIO_NXP_S32_RESERVED_PIN_MASK(n)					\  argument
498 	(GENMASK(DT_INST_PROP_BY_IDX(n, gpio_reserved_ranges, 0) +		\
499 			DT_INST_PROP_BY_IDX(n, gpio_reserved_ranges, 1) - 1,	\
500 		 DT_INST_PROP_BY_IDX(n, gpio_reserved_ranges, 0)		\
503 #define GPIO_NXP_S32_PORT_PIN_MASK(n)						\  argument
504 	COND_CODE_1(DT_INST_NODE_HAS_PROP(n, gpio_reserved_ranges),		\
505 		(GPIO_PORT_PIN_MASK_FROM_DT_INST(n)				\
506 			& ~(GPIO_NXP_S32_RESERVED_PIN_MASK(n))),		\
507 		(GPIO_PORT_PIN_MASK_FROM_DT_INST(n)))
510 #define GPIO_NXP_S32_EIRQ_NODE(n)						\  argument
511 	DT_INST_PHANDLE(n, interrupt_parent)
513 #define GPIO_NXP_S32_EIRQ_PIN_LINE(idx, n)					\  argument
514 	DT_INST_IRQ_BY_IDX(n, idx, gpio_pin),					\
515 	DT_INST_IRQ_BY_IDX(n, idx, eirq_line)					\
517 #define GPIO_NXP_S32_SET_EIRQ_INFO(n)						\  argument
518 	BUILD_ASSERT((DT_NODE_HAS_PROP(DT_DRV_INST(n), interrupt_parent) ==	\
519 			DT_NODE_HAS_PROP(DT_DRV_INST(n), interrupts)),		\
520 			"interrupts and interrupt-parent must be set when "	\
522 	IF_ENABLED(DT_NODE_HAS_STATUS_OKAY(GPIO_NXP_S32_EIRQ_NODE(n)), (	\
523 		static uint8_t gpio_nxp_s32_eirq_data_##n[] = {			\
524 			LISTIFY(DT_NUM_IRQS(DT_DRV_INST(n)),			\
525 				GPIO_NXP_S32_EIRQ_PIN_LINE, (,), n)		\
527 		static struct gpio_nxp_s32_irq_config gpio_nxp_s32_eirq_##n = {	\
528 			.ctrl = DEVICE_DT_GET(GPIO_NXP_S32_EIRQ_NODE(n)),	\
529 			.map_cnt = DT_NUM_IRQS(DT_DRV_INST(n)),			\
531 				gpio_nxp_s32_eirq_data_##n,			\
535 #define GPIO_NXP_S32_GET_EIRQ_INFO(n)						\  argument
536 	.eirq_info = UTIL_AND(DT_NODE_HAS_STATUS_OKAY(GPIO_NXP_S32_EIRQ_NODE(n)),\
537 				&gpio_nxp_s32_eirq_##n),
539 #define GPIO_NXP_S32_SET_EIRQ_INFO(n)  argument
540 #define GPIO_NXP_S32_GET_EIRQ_INFO(n)  argument
544 #define GPIO_NXP_S32_WKPU_NODE(n) DT_INST_PHANDLE(n, nxp_wkpu)  argument
546 #define GPIO_NXP_S32_SET_WKPU_INFO(n)						\  argument
547 	BUILD_ASSERT((DT_INST_NODE_HAS_PROP(n, nxp_wkpu) ==			\
548 			DT_INST_NODE_HAS_PROP(n, nxp_wkpu_interrupts)),		\
549 			"nxp,wkpu and nxp,wkpu-interrupts must be provided");	\
550 	IF_ENABLED(DT_NODE_HAS_STATUS_OKAY(GPIO_NXP_S32_WKPU_NODE(n)), (	\
551 		static uint8_t gpio_nxp_s32_wkpu_data_##n[] =			\
552 			DT_INST_PROP(n, nxp_wkpu_interrupts);			\
553 		static struct gpio_nxp_s32_irq_config gpio_nxp_s32_wkpu_##n = {	\
554 			.ctrl = DEVICE_DT_GET(GPIO_NXP_S32_WKPU_NODE(n)),	\
555 			.map_cnt = sizeof(gpio_nxp_s32_wkpu_data_##n) /		\
558 				gpio_nxp_s32_wkpu_data_##n,			\
562 #define GPIO_NXP_S32_GET_WKPU_INFO(n)						\  argument
563 	.wkpu_info = UTIL_AND(DT_NODE_HAS_STATUS_OKAY(GPIO_NXP_S32_WKPU_NODE(n)),\
564 				&gpio_nxp_s32_wkpu_##n)
566 #define GPIO_NXP_S32_SET_WKPU_INFO(n)  argument
567 #define GPIO_NXP_S32_GET_WKPU_INFO(n)  argument
570 #define GPIO_NXP_S32_DEVICE_INIT(n)						\  argument
571 	GPIO_NXP_S32_SET_EIRQ_INFO(n)						\
572 	GPIO_NXP_S32_SET_WKPU_INFO(n)						\
573 	static const struct gpio_nxp_s32_config gpio_nxp_s32_config_##n = {	\
575 			.port_pin_mask = GPIO_NXP_S32_PORT_PIN_MASK(n),		\
577 		.gpio_base = DT_INST_REG_ADDR_BY_NAME(n, pgpdo),		\
578 		.port_base = DT_INST_REG_ADDR_BY_NAME(n, mscr),			\
579 		GPIO_NXP_S32_GET_EIRQ_INFO(n)					\
580 		GPIO_NXP_S32_GET_WKPU_INFO(n)					\
582 	static struct gpio_nxp_s32_data gpio_nxp_s32_data_##n;			\
583 	static int gpio_nxp_s32_init_##n(const struct device *dev)		\
587 	DEVICE_DT_INST_DEFINE(n,						\
588 			gpio_nxp_s32_init_##n,					\
590 			&gpio_nxp_s32_data_##n,					\
591 			&gpio_nxp_s32_config_##n,				\