4  * SPDX-License-Identifier: Apache-2.0
21 	((__IO uint32_t *)(GPIO_PARIN_BASE + (config->port_num << 2)))
24 	((__IO uint32_t *)(GPIO_PAROUT_BASE + (config->port_num << 2)))
52  * notes: The GPIO parallel output bits are read-only until the
53  * Alternate-Output-Disable (AOD) bit is set in the pin's control
65 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_configure()
68 	uint32_t mask = 0U;  in gpio_xec_configure()  local
71 	if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {  in gpio_xec_configure()
72 		return -EINVAL;  in gpio_xec_configure()
78 		return -ENOTSUP;  in gpio_xec_configure()
87 	mask |= MCHP_GPIO_CTRL_DIR_MASK;  in gpio_xec_configure()
88 	mask |= MCHP_GPIO_CTRL_INPAD_DIS_MASK;  in gpio_xec_configure()
89 	mask |= MCHP_GPIO_CTRL_PWRG_MASK;  in gpio_xec_configure()
90 	mask |= MCHP_GPIO_CTRL_AOD_MASK;  in gpio_xec_configure()
92 	current_pcr1 = config->pcr1_base + pin;  in gpio_xec_configure()
96 		*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;  in gpio_xec_configure()
107 	/* Figure out the pullup/pulldown configuration and keep it in the  in gpio_xec_configure()
110 	mask |= MCHP_GPIO_CTRL_PUD_MASK;  in gpio_xec_configure()
113 		/* Enable the pull and select the pullup resistor. */  in gpio_xec_configure()
120 	/* Push-pull or open drain */  in gpio_xec_configure()
121 	mask |= MCHP_GPIO_CTRL_BUFT_MASK;  in gpio_xec_configure()
127 		/* Push-pull */  in gpio_xec_configure()
132 		mask |= MCHP_GPIO_CTRL_OUTV_HI;  in gpio_xec_configure()
154 	*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;  in gpio_xec_configure()
166 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_pin_interrupt_configure()
169 	uint32_t mask = 0U;  in gpio_xec_pin_interrupt_configure()  local
173 	if ((valid_ctrl_masks[config->port_num] & BIT(pin)) == 0U) {  in gpio_xec_pin_interrupt_configure()
174 		return -EINVAL;  in gpio_xec_pin_interrupt_configure()
179 	    ((config->flags & GPIO_INT_ENABLE) == 0U)) {  in gpio_xec_pin_interrupt_configure()
180 		return -ENOTSUP;  in gpio_xec_pin_interrupt_configure()
184 	MCHP_GIRQ_ENCLR(config->girq_id) = BIT(pin);  in gpio_xec_pin_interrupt_configure()
186 	/* Assemble mask for level/edge triggered interrupts */  in gpio_xec_pin_interrupt_configure()
187 	mask |= MCHP_GPIO_CTRL_IDET_MASK;  in gpio_xec_pin_interrupt_configure()
215 				return -EINVAL;  in gpio_xec_pin_interrupt_configure()
225 	current_pcr1 = config->pcr1_base + pin;  in gpio_xec_pin_interrupt_configure()
226 	*current_pcr1 = (*current_pcr1 & ~mask) | pcr1;  in gpio_xec_pin_interrupt_configure()
236 		MCHP_GIRQ_SRC_CLR(config->girq_id, pin);  in gpio_xec_pin_interrupt_configure()
237 		MCHP_GIRQ_ENSET(config->girq_id) = BIT(pin);  in gpio_xec_pin_interrupt_configure()
244 					uint32_t mask,  in gpio_xec_port_set_masked_raw()  argument
247 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port_set_masked_raw()
252 	*gpio_base = (*gpio_base & ~mask) | (mask & value);  in gpio_xec_port_set_masked_raw()
257 static int gpio_xec_port_set_bits_raw(const struct device *dev, uint32_t mask)  in gpio_xec_port_set_bits_raw()  argument
259 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port_set_bits_raw()
264 	*gpio_base |= mask;  in gpio_xec_port_set_bits_raw()
270 					uint32_t mask)  in gpio_xec_port_clear_bits_raw()  argument
272 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port_clear_bits_raw()
277 	*gpio_base &= ~mask;  in gpio_xec_port_clear_bits_raw()
282 static int gpio_xec_port_toggle_bits(const struct device *dev, uint32_t mask)  in gpio_xec_port_toggle_bits()  argument
284 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port_toggle_bits()
289 	*gpio_base ^= mask;  in gpio_xec_port_toggle_bits()
296 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port_get_raw()
309 	struct gpio_xec_data *data = dev->data;  in gpio_xec_manage_callback()
311 	gpio_manage_callback(&data->callbacks, callback, set);  in gpio_xec_manage_callback()
318 	const struct gpio_xec_config *config = dev->config;  in gpio_gpio_xec_port_isr()
319 	struct gpio_xec_data *data = dev->data;  in gpio_gpio_xec_port_isr()
325 	girq_result = MCHP_GIRQ_RESULT(config->girq_id);  in gpio_gpio_xec_port_isr()
328 	REG32(MCHP_GIRQ_SRC_ADDR(config->girq_id)) = girq_result;  in gpio_gpio_xec_port_isr()
330 	gpio_fire_callbacks(&data->callbacks, dev, girq_result);  in gpio_gpio_xec_port_isr()
374 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port000_036_init()
377 	MCHP_GIRQ_BLK_SETEN(config->girq_id);  in gpio_xec_port000_036_init()
420 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port040_076_init()
423 	MCHP_GIRQ_BLK_SETEN(config->girq_id);  in gpio_xec_port040_076_init()
466 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port100_136_init()
469 	MCHP_GIRQ_BLK_SETEN(config->girq_id);  in gpio_xec_port100_136_init()
512 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port140_176_init()
515 	MCHP_GIRQ_BLK_SETEN(config->girq_id);  in gpio_xec_port140_176_init()
558 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port200_236_init()
561 	MCHP_GIRQ_BLK_SETEN(config->girq_id);  in gpio_xec_port200_236_init()
604 	const struct gpio_xec_config *config = dev->config;  in gpio_xec_port240_276_init()
607 	MCHP_GIRQ_BLK_SETEN(config->girq_id);  in gpio_xec_port240_276_init()