5  * SPDX-License-Identifier: Apache-2.0
14  * This driver allows to configure the GPIOs found on the LPC11U6x MCUs.
78  * This structure is included by all the per-port private configuration.
108 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_pin_configure()
110 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);  in gpio_lpc11u6x_pin_configure()
111 	uint8_t port_num = config->port_num;  in gpio_lpc11u6x_pin_configure()
115 	if (pin >= config->ngpios) {  in gpio_lpc11u6x_pin_configure()
116 		return -EINVAL;  in gpio_lpc11u6x_pin_configure()
121 	 * 0. They still can be configured as GPIOs but only in open drain mode  in gpio_lpc11u6x_pin_configure()
122 	 * and with no pull-down or pull-up resistor enabled.  in gpio_lpc11u6x_pin_configure()
127 		return -EINVAL;  in gpio_lpc11u6x_pin_configure()
131 	 * For PIO0_0 and PIO0_[10-15] function 1 enables GPIO mode. For all  in gpio_lpc11u6x_pin_configure()
145 			return -ENOTSUP;  in gpio_lpc11u6x_pin_configure()
164 	config->iocon_base[offset] = func;  in gpio_lpc11u6x_pin_configure()
168 		gpio_regs->set[port_num] |= BIT(pin);  in gpio_lpc11u6x_pin_configure()
172 		gpio_regs->clr[port_num] |= BIT(pin);  in gpio_lpc11u6x_pin_configure()
176 	 * TODO: maybe configure the STARTERP0 register to allow wake-up from  in gpio_lpc11u6x_pin_configure()
177 	 * deep-sleep or power-down modes.  in gpio_lpc11u6x_pin_configure()
181 	WRITE_BIT(gpio_regs->dir[port_num], pin, flags & GPIO_OUTPUT);  in gpio_lpc11u6x_pin_configure()
189 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_port_get_raw()
191 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);  in gpio_lpc11u6x_port_get_raw()
193 	*value = gpio_regs->pin[config->port_num];  in gpio_lpc11u6x_port_get_raw()
202 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_port_set_masked_raw()
204 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);  in gpio_lpc11u6x_port_set_masked_raw()
205 	uint8_t port_num = config->port_num;  in gpio_lpc11u6x_port_set_masked_raw()
208 	orig_mask = gpio_regs->mask[port_num];  in gpio_lpc11u6x_port_set_masked_raw()
210 	gpio_regs->mask[port_num] = ~mask;  in gpio_lpc11u6x_port_set_masked_raw()
213 	gpio_regs->mpin[port_num] = value;  in gpio_lpc11u6x_port_set_masked_raw()
216 	gpio_regs->mask[port_num] = orig_mask;  in gpio_lpc11u6x_port_set_masked_raw()
225 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_port_set_bits_raw()
227 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);  in gpio_lpc11u6x_port_set_bits_raw()
229 	gpio_regs->set[config->port_num] = pins;  in gpio_lpc11u6x_port_set_bits_raw()
237 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_port_clear_bits_raw()
239 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);  in gpio_lpc11u6x_port_clear_bits_raw()
241 	gpio_regs->clr[config->port_num] = pins;  in gpio_lpc11u6x_port_clear_bits_raw()
249 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_port_toggle_bits()
251 		(config->shared->gpio_base + LPC11U6X_GPIO_REGS);  in gpio_lpc11u6x_port_toggle_bits()
253 	gpio_regs->not[config->port_num] = pins;  in gpio_lpc11u6x_port_toggle_bits()
263  *                 with the INTPIN register (included in the PINTSEL register).
266  * @retval -EBUSY  All the interrupt lines are already attached.
272 	int ret = -EBUSY;  in pintsel_attach()
274 		(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);  in pintsel_attach()
276 	for (irq = 0; irq < shared->nirqs; irq++) {  in pintsel_attach()
299  *                 with the INTPIN register (included in the PINTSEL register).
302  * @retval -EINVAL No attached interrupt found for the requested GPIO.
309 		(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);  in pintsel_detach()
311 	for (irq = 0; irq < shared->nirqs; irq++) {  in pintsel_detach()
317 	return -EINVAL;  in pintsel_detach()
323 						 enum gpio_int_trig trig)  in gpio_lpc11u6x_pin_interrupt_configure()  argument
325 	const struct gpio_lpc11u6x_config *config = port->config;  in gpio_lpc11u6x_pin_interrupt_configure()
327 		(config->shared->gpio_base + LPC11U6X_PINT_REGS);  in gpio_lpc11u6x_pin_interrupt_configure()
331 	if (pin >= config->ngpios) {  in gpio_lpc11u6x_pin_interrupt_configure()
332 		return -EINVAL;  in gpio_lpc11u6x_pin_interrupt_configure()
340 	if (config->port_num == 2 && pin > 7) {  in gpio_lpc11u6x_pin_interrupt_configure()
341 		return -ENOTSUP;  in gpio_lpc11u6x_pin_interrupt_configure()
346 	 * compatible with the INTPIN register (included in the PINTSEL  in gpio_lpc11u6x_pin_interrupt_configure()
350 	if (config->port_num == 1) {  in gpio_lpc11u6x_pin_interrupt_configure()
352 	} else if (config->port_num == 2) {  in gpio_lpc11u6x_pin_interrupt_configure()
357 		irq = pintsel_detach(config->shared, intpin);  in gpio_lpc11u6x_pin_interrupt_configure()
359 		irq = pintsel_attach(config->shared, intpin);  in gpio_lpc11u6x_pin_interrupt_configure()
367 		pint_regs->isel &= ~BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
368 		pint_regs->cienr |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
369 		pint_regs->cienf |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
373 		pint_regs->isel &= ~BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
375 		if (trig & GPIO_INT_TRIG_LOW) {  in gpio_lpc11u6x_pin_interrupt_configure()
376 			pint_regs->sienf |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
378 			pint_regs->cienf |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
380 		if (trig & GPIO_INT_TRIG_HIGH) {  in gpio_lpc11u6x_pin_interrupt_configure()
381 			pint_regs->sienr |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
383 			pint_regs->cienr |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
388 		pint_regs->isel |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
390 		if (trig & GPIO_INT_TRIG_LOW) {  in gpio_lpc11u6x_pin_interrupt_configure()
391 			pint_regs->cienf |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
393 			pint_regs->sienf |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
396 		pint_regs->sienr |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
399 		return -ENOTSUP;  in gpio_lpc11u6x_pin_interrupt_configure()
403 	pint_regs->ist |= BIT(irq);  in gpio_lpc11u6x_pin_interrupt_configure()
411 	struct gpio_lpc11u6x_data *data = port->data;  in gpio_lpc11u6x_manage_callback()
413 	return gpio_manage_callback(&data->cb_list, cb, set);  in gpio_lpc11u6x_manage_callback()
420 	return -ENOTSUP;  in gpio_lpc11u6x_get_pending_int()
428 		(shared->gpio_base + LPC11U6X_PINT_REGS);  in gpio_lpc11u6x_isr()
430 		(uint32_t *) (shared->syscon_base + LPC11U6X_PINTSEL_REGS);  in gpio_lpc11u6x_isr()
436 	for (irq = 0; irq < shared->nirqs; irq++) {  in gpio_lpc11u6x_isr()
439 		if ((pint_regs->ist & BIT(irq)) == 0) {  in gpio_lpc11u6x_isr()
444 		pint_regs->ist |= BIT(irq);  in gpio_lpc11u6x_isr()
447 		 * Look in the PINTSEL register to retrieve the "intpin" value  in gpio_lpc11u6x_isr()
456 			pins[1] |= BIT(intpin - 24);  in gpio_lpc11u6x_isr()
458 			pins[2] |= BIT(intpin - 56);  in gpio_lpc11u6x_isr()
465 		data = port->data;  in gpio_lpc11u6x_isr()
466 		gpio_fire_callbacks(&data->cb_list, port, pins[0]);  in gpio_lpc11u6x_isr()
472 		data = port->data;  in gpio_lpc11u6x_isr()
473 		gpio_fire_callbacks(&data->cb_list, port, pins[1]);  in gpio_lpc11u6x_isr()
479 		data = port->data;  in gpio_lpc11u6x_isr()
480 		gpio_fire_callbacks(&data->cb_list, port, pins[2]);  in gpio_lpc11u6x_isr()
520 	const struct gpio_lpc11u6x_config *config = dev->config;  in gpio_lpc11u6x_init()
529 	if (!device_is_ready(config->shared->clock_dev)) {  in gpio_lpc11u6x_init()
530 		return -ENODEV;  in gpio_lpc11u6x_init()
534 	ret = clock_control_on(config->shared->clock_dev, config->shared->clock_subsys);  in gpio_lpc11u6x_init()