Lines Matching +full:gpio_config +full:-
2 * Copyright (c) 2019-2021 Antmicro <www.antmicro.com>
5 * SPDX-License-Identifier: Apache-2.0
58 ((const struct gpio_litex_cfg *)(dev)->config)
67 regv = litex_read(config->reg_addr, config->reg_size); in set_bit()
69 litex_write(config->reg_addr, config->reg_size, new_regv); in set_bit()
74 int regv = litex_read(config->reg_addr, config->reg_size); in get_bit()
81 litex_write(config->reg_addr, config->reg_size, value); in set_port()
86 int regv = litex_read(config->reg_addr, config->reg_size); in get_port()
88 return (regv & BIT_MASK(config->nr_gpios)); in get_port()
96 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_configure() local
99 return -ENOTSUP; in gpio_litex_configure()
104 return -ENOTSUP; in gpio_litex_configure()
107 return -ENOTSUP; in gpio_litex_configure()
111 if (!gpio_config->port_is_output) { in gpio_litex_configure()
113 return -EINVAL; in gpio_litex_configure()
117 set_bit(gpio_config, pin, GPIO_HIGH); in gpio_litex_configure()
119 set_bit(gpio_config, pin, GPIO_LOW); in gpio_litex_configure()
122 if (gpio_config->port_is_output) { in gpio_litex_configure()
124 return -EINVAL; in gpio_litex_configure()
134 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_port_get_raw() local
136 *value = get_port(gpio_config); in gpio_litex_port_get_raw()
144 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_port_set_masked_raw() local
147 port_val = get_port(gpio_config); in gpio_litex_port_set_masked_raw()
149 set_port(gpio_config, port_val); in gpio_litex_port_set_masked_raw()
157 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_port_set_bits_raw() local
160 port_val = get_port(gpio_config); in gpio_litex_port_set_bits_raw()
162 set_port(gpio_config, port_val); in gpio_litex_port_set_bits_raw()
170 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_port_clear_bits_raw() local
173 port_val = get_port(gpio_config); in gpio_litex_port_clear_bits_raw()
175 set_port(gpio_config, port_val); in gpio_litex_port_clear_bits_raw()
183 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_port_toggle_bits() local
186 port_val = get_port(gpio_config); in gpio_litex_port_toggle_bits()
188 set_port(gpio_config, port_val); in gpio_litex_port_toggle_bits()
195 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_irq_handler() local
196 struct gpio_litex_data *data = dev->data; in gpio_litex_irq_handler()
199 litex_read(gpio_config->ev_pending_addr, gpio_config->reg_size); in gpio_litex_irq_handler()
201 litex_read(gpio_config->ev_enable_addr, gpio_config->reg_size); in gpio_litex_irq_handler()
204 litex_write(gpio_config->ev_pending_addr, gpio_config->reg_size, in gpio_litex_irq_handler()
207 gpio_fire_callbacks(&data->cb, dev, int_status & ev_enabled); in gpio_litex_irq_handler()
213 struct gpio_litex_data *data = dev->data; in gpio_litex_manage_callback()
215 return gpio_manage_callback(&data->cb, callback, set); in gpio_litex_manage_callback()
223 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_pin_interrupt_configure() local
225 if (gpio_config->port_is_output == true) { in gpio_litex_pin_interrupt_configure()
226 return -ENOTSUP; in gpio_litex_pin_interrupt_configure()
230 uint8_t ev_enabled = litex_read(gpio_config->ev_enable_addr, in gpio_litex_pin_interrupt_configure()
231 gpio_config->reg_size); in gpio_litex_pin_interrupt_configure()
232 uint8_t ev_mode = litex_read(gpio_config->ev_mode_addr, in gpio_litex_pin_interrupt_configure()
233 gpio_config->reg_size); in gpio_litex_pin_interrupt_configure()
234 uint8_t ev_edge = litex_read(gpio_config->ev_edge_addr, in gpio_litex_pin_interrupt_configure()
235 gpio_config->reg_size); in gpio_litex_pin_interrupt_configure()
237 litex_write(gpio_config->ev_enable_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
242 litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
244 litex_write(gpio_config->ev_edge_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
248 litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
250 litex_write(gpio_config->ev_edge_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
254 litex_write(gpio_config->ev_mode_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
261 uint8_t ev_enabled = litex_read(gpio_config->ev_enable_addr, in gpio_litex_pin_interrupt_configure()
262 gpio_config->reg_size); in gpio_litex_pin_interrupt_configure()
263 litex_write(gpio_config->ev_enable_addr, gpio_config->reg_size, in gpio_litex_pin_interrupt_configure()
268 return -ENOTSUP; in gpio_litex_pin_interrupt_configure()
275 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); in gpio_litex_port_get_direction() local
277 map &= gpio_config->port_pin_mask; in gpio_litex_port_get_direction()
280 *inputs = map & (!gpio_config->port_is_output); in gpio_litex_port_get_direction()
284 *outputs = map & (gpio_config->port_is_output); in gpio_litex_port_get_direction()
344 const struct gpio_litex_cfg *gpio_config = DEV_GPIO_CFG(dev); \
350 if (gpio_config->nr_gpios > max_gpios_can_fit) { \
352 return -EINVAL; \