4  * SPDX-License-Identifier: Apache-2.0
11 #include <zephyr/dt-bindings/gpio/ite-it8xxx2-gpio.h>
12 #include <zephyr/dt-bindings/interrupt-controller/ite-intc.h>
57 	((struct gpio_ite_data *)(dev)->data)
60 	((const struct gpio_ite_cfg *)(dev)->config)
63  * Convert wake-up controller (WUC) group to the corresponding wake-up edge
73 	 * From WUESR1-WUESR4, the address increases by ones. From WUESR5 on  in wuesr()
77 			(volatile uint8_t *)(IT8XXX2_WUC_WUESR1 + grp-1) :  in wuesr()
78 			(volatile uint8_t *)(IT8XXX2_WUC_WUESR5 + 4*(grp-5));  in wuesr()
82  * Convert wake-up controller (WUC) group to the corresponding wake-up edge
92 	 * From WUEMR1-WUEMR4, the address increases by ones. From WUEMR5 on  in wuemr()
96 			(volatile uint8_t *)(IT8XXX2_WUC_WUEMR1 + grp-1) :  in wuemr()
97 			(volatile uint8_t *)(IT8XXX2_WUC_WUEMR5 + 4*(grp-5));  in wuemr()
101  * Convert wake-up controller (WUC) group to the corresponding wake-up both edge
111 	 * From WUBEMR1-WUBEMR4, the address increases by ones. From WUBEMR5 on  in wubemr()
115 			(volatile uint8_t *)(IT8XXX2_WUC_WUBEMR1 + grp-1) :  in wubemr()
116 			(volatile uint8_t *)(IT8XXX2_WUC_WUBEMR5 + 4*(grp-5));  in wubemr()
133 	[IT8XXX2_IRQ_WU23] = {BIT(6), 2, BIT(3)},
141 	[IT8XXX2_IRQ_WU53] = {BIT(3), 5, BIT(3)},
149 	[IT8XXX2_IRQ_WU63] = {BIT(3), 6, BIT(3)},
157 	[IT8XXX2_IRQ_WU73] = {BIT(3), 7, BIT(3)},
162 	[IT8XXX2_IRQ_WU80] = {BIT(3), 8, BIT(0)},
165 	[IT8XXX2_IRQ_WU83] = {BIT(6), 8, BIT(3)},
173 	[IT8XXX2_IRQ_WU91] = {BIT(0), 9, BIT(3)},
181 	[IT8XXX2_IRQ_WU99] = {BIT(3), 10, BIT(3)},
185 	[IT8XXX2_IRQ_WU103] = {BIT(3), 10, BIT(7)},
189 	[IT8XXX2_IRQ_WU107] = {BIT(1), 11, BIT(3)},
190 	[IT8XXX2_IRQ_WU108] = {BIT(3), 11, BIT(4)},
192 	[IT8XXX2_IRQ_WU110] = {BIT(3), 11, BIT(6)},
197 	[IT8XXX2_IRQ_WU115] = {BIT(0), 12, BIT(3)},
204 	[IT8XXX2_IRQ_WU122] = {BIT(3), 13, BIT(2)},
205 	[IT8XXX2_IRQ_WU123] = {BIT(3), 13, BIT(3)},
212 	[IT8XXX2_IRQ_WU131] = {BIT(3), 14, BIT(3)},
220 	[IT8XXX2_IRQ_WU139] = {BIT(3), 15, BIT(3)},
228 	[IT8XXX2_IRQ_WU147] = {BIT(3), 16, BIT(3)},
239 		(uint8_t)(DT_REG_ADDR(DT_NODELABEL(label)) - \
253 		[3] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(1)},
263 		[6] = {IT8XXX2_GPIO_GCR24_OFFSET, BIT(3)},
264 		[7] = {IT8XXX2_GPIO_GCR19_OFFSET, BIT(3)} },
269 		[3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(7)},
279 		[5] = {IT8XXX2_GPIO_GCR22_OFFSET, BIT(3)},
281 		[7] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(3)} },
286 		[3] = {IT8XXX2_GPIO_GCR20_OFFSET, BIT(1)},
294 		[2] = {IT8XXX2_GPIO_GCR28_OFFSET, BIT(3)},
295 		[6] = {IT8XXX2_GPIO_GCR21_OFFSET, BIT(3)} },
303 		[0] = {IT8XXX2_GPIO_GCR27_OFFSET, BIT(3)},
306 		[3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(6)},
315 		[3] = {IT8XXX2_GPIO_GCR23_OFFSET, BIT(3)},
324 		[3] = {IT8XXX2_GPIO_GCR26_OFFSET, BIT(3)},
333 		[3] = {IT8XXX2_GPIO_GCR25_OFFSET, BIT(3)},
339 	 * M group's voltage level is according to chip's VCC is connected
346 		[3] = {IT8XXX2_GPIO_GCR30_OFFSET, BIT(4)},
361 	volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;  in gpio_ite_configure()
362 	volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);  in gpio_ite_configure()
363 	volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;  in gpio_ite_configure()
368 	__ASSERT(gpio_config->index < GPIO_GROUP_COUNT,  in gpio_ite_configure()
374 		return -ENOTSUP;  in gpio_ite_configure()
380 		 * Since not all GPIOs can be to configured as tri-state,  in gpio_ite_configure()
386 			LOG_ERR("Cannot config GPIO-%c%d as tri-state",  in gpio_ite_configure()
387 				(gpio_config->index + 'A'), pin);  in gpio_ite_configure()
388 			return -ENOTSUP;  in gpio_ite_configure()
409 			gpio_1p8v[gpio_config->index][pin].offset);  in gpio_ite_configure()
410 	mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;  in gpio_ite_configure()
422 			return -EINVAL;  in gpio_ite_configure()
467 	volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;  in gpio_ite_get_config()
468 	volatile uint8_t *reg_gpcr = (uint8_t *)(gpio_config->reg_gpcr + pin);  in gpio_ite_get_config()
469 	volatile uint8_t *reg_gpotr = (uint8_t *)gpio_config->reg_gpotr;  in gpio_ite_get_config()
475 	__ASSERT(gpio_config->index < GPIO_GROUP_COUNT,  in gpio_ite_get_config()
478 	/* push-pull or open-drain */  in gpio_ite_get_config()
485 			gpio_1p8v[gpio_config->index][pin].offset);  in gpio_ite_get_config()
491 		mask_1p8v = gpio_1p8v[gpio_config->index][pin].mask_1p8v;  in gpio_ite_get_config()
534 	volatile uint8_t *reg_gpdmr = (uint8_t *)gpio_config->reg_gpdmr;  in gpio_ite_port_get_raw()
547 	volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;  in gpio_ite_port_set_masked_raw()
559 	volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;  in gpio_ite_port_set_bits_raw()
571 	volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;  in gpio_ite_port_clear_bits_raw()
583 	volatile uint8_t *reg_gpdr = (uint8_t *)gpio_config->reg_gpdr;  in gpio_ite_port_toggle_bits()
597 	return gpio_manage_callback(&data->callbacks, callback, set);  in gpio_ite_manage_callback()
610 		gpio_fire_callbacks(&data->callbacks, dev, gpio_mask);  in gpio_ite_isr()
620 	uint8_t gpio_irq = gpio_config->gpio_irq[pin];
640 		return -ENOTSUP;
700 	.reg_gpotr = DT_INST_REG_ADDR_BY_IDX(inst, 3),             \
701 	.index = (uint8_t)(DT_INST_REG_ADDR(inst) -                \
706 	.gpio_irq[3] = DT_INST_IRQ_BY_IDX(inst, 3, irq),           \