2  * Copyright (c) 2018-2019 Intel Corporation
4  * SPDX-License-Identifier: Apache-2.0
17  * Due to GPIO callback only allowing 32 pins (as a 32-bit mask) at once,
18  * each set is further sub-divided into multiple devices, so
30 #include <zephyr/dt-bindings/interrupt-controller/intel-ioapic.h>
92 	((const struct gpio_intel_config *)(_dev)->config)
93 #define DEV_DATA(_dev) ((struct gpio_intel_data *)(_dev)->data)
130 #define REG_GPI_INT_STS_BASE_GET(data) (data)->intr_stat_reg
132 #define REG_GPI_INT_EN_BASE_GET(data) (data)->intr_stat_reg + 0x20
136 #define GPIO_PAD_OWNERSHIP_GET(data, pin, offset) (data)->pad_owner_reg + (((pin) / 8) * 0x4)
138 #define REG_PAD_HOST_SW_OWNER_GET(data) (data)->host_owner_reg
144 #define GPIO_GET_PIN_MAX(dev) ((struct gpio_intel_data *)(dev)->data)->num_pins
145 #else /* Non-ACPI */
152 #define PIN_OFFSET_GET(dev) ((const struct gpio_intel_config *)(dev)->config)->pin_offset
158 #define GPIO_BASE_GET(cdf) GPIO_BASE(((const struct gpio_intel_config *)(dev)->config))
162 #define GPIO_GET_PIN_MAX(dev) ((const struct gpio_intel_config *)(dev)->config)->num_pins
188 	struct gpio_intel_data *data = dev->data;  in check_perm()
208 	offset = data->pad_base + (raw_pin << 4);  in check_perm()
235 	cfg = dev->config;  in gpio_intel_isr()
236 	data = dev->data;  in gpio_intel_isr()
242 	SYS_SLIST_FOR_EACH_CONTAINER_SAFE(&data->cb, cb, tmp, node) {  in gpio_intel_isr()
243 		cur_mask = int_sts & cb->pin_mask;  in gpio_intel_isr()
246 			__ASSERT(cb->handler, "No callback handler!");  in gpio_intel_isr()
247 			cb->handler(dev, cb, cur_mask);  in gpio_intel_isr()
258 	struct gpio_intel_data *data = dev->data;  in gpio_intel_config()
261 	/* Only support push-pull mode */  in gpio_intel_config()
263 		return -ENOTSUP;  in gpio_intel_config()
271 		return -EINVAL;  in gpio_intel_config()
275 	reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in gpio_intel_config()
308 	/* pull-up or pull-down */  in gpio_intel_config()
333 	struct gpio_intel_data *data = dev->data;  in gpio_intel_pin_interrupt_configure()
337 	/* no double-edge triggering according to data sheet */  in gpio_intel_pin_interrupt_configure()
339 		return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
347 		return -EINVAL;  in gpio_intel_pin_interrupt_configure()
356 	reg = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in gpio_intel_pin_interrupt_configure()
370 	/* clear level/edge configuration bits */  in gpio_intel_pin_interrupt_configure()
379 			return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
390 			return -ENOTSUP;  in gpio_intel_pin_interrupt_configure()
397 			/* edge trigger */  in gpio_intel_pin_interrupt_configure()
425 	struct gpio_intel_data *data = dev->data;  in gpio_intel_manage_callback()
427 	return gpio_manage_callback(&data->cb, callback, set);  in gpio_intel_manage_callback()
430 static int port_get_raw(const struct device *dev, uint32_t mask,  in port_get_raw()  argument
434 	struct gpio_intel_data *data = dev->data;  in port_get_raw()
444 	while (mask != 0U) {  in port_get_raw()
445 		pin = find_lsb_set(mask) - 1;  in port_get_raw()
451 		mask &= ~BIT(pin);  in port_get_raw()
459 		reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in port_get_raw()
470 static int port_set_raw(const struct device *dev, uint32_t mask,  in port_set_raw()  argument
473 	struct gpio_intel_data *data = dev->data;  in port_set_raw()
476 	while (mask != 0) {  in port_set_raw()
477 		pin = find_lsb_set(mask) - 1;  in port_set_raw()
483 		mask &= ~BIT(pin);  in port_set_raw()
491 		reg_addr = regs(dev) + data->pad_base + (raw_pin * PIN_OFFSET);  in port_set_raw()
507 					  uint32_t mask,  in gpio_intel_port_set_masked_raw()  argument
512 	port_get_raw(dev, mask, &port_val, true);  in gpio_intel_port_set_masked_raw()
514 	port_val = (port_val & ~mask) | (mask & value);  in gpio_intel_port_set_masked_raw()
516 	port_set_raw(dev, mask, port_val);  in gpio_intel_port_set_masked_raw()
522 					uint32_t mask)  in gpio_intel_port_set_bits_raw()  argument
524 	return gpio_intel_port_set_masked_raw(dev, mask, mask);  in gpio_intel_port_set_bits_raw()
528 					  uint32_t mask)  in gpio_intel_port_clear_bits_raw()  argument
530 	return gpio_intel_port_set_masked_raw(dev, mask, 0);  in gpio_intel_port_clear_bits_raw()
534 				       uint32_t mask)  in gpio_intel_port_toggle_bits()  argument
538 	port_get_raw(dev, mask, &port_val, true);  in gpio_intel_port_toggle_bits()
540 	port_val ^= mask;  in gpio_intel_port_toggle_bits()
542 	port_set_raw(dev, mask, port_val);  in gpio_intel_port_toggle_bits()
571 	struct gpio_intel_data *data = dev->data;  in gpio_intel_acpi_enum()
578 	device_map(&data->reg_base, res.reg_base, res.len, K_MEM_CACHE_NONE);  in gpio_intel_acpi_enum()
580 	data->num_pins = res.num_pins;  in gpio_intel_acpi_enum()
581 	data->pad_owner_reg = res.pad_owner_reg;  in gpio_intel_acpi_enum()
582 	data->host_owner_reg = res.host_owner_reg;  in gpio_intel_acpi_enum()
583 	data->intr_stat_reg = res.intr_stat_reg;  in gpio_intel_acpi_enum()
584 	data->base_num = res.base_num;  in gpio_intel_acpi_enum()
585 	data->pad_base = res.pad_base;  in gpio_intel_acpi_enum()
625 	struct gpio_intel_data *data = dev->data;  in gpio_intel_dts_init()
632 	 * into 32-pin blocks so each block has a GPIO driver instance.  in gpio_intel_dts_init()
636 	 * So when mapping the address, the lowest 8-bit needs to be  in gpio_intel_dts_init()
641 	const struct gpio_intel_config *cfg = dev->config;  in gpio_intel_dts_init()
643 	device_map(&data->reg_base,  in gpio_intel_dts_init()
644 		   cfg->reg_base.phys_addr & ~0xFFU,  in gpio_intel_dts_init()
645 		   cfg->reg_base.size,  in gpio_intel_dts_init()
650 	data->pad_base = pad_base(dev);  in gpio_intel_dts_init()
659 			    DT_INST_IRQ(0, sense));  in gpio_intel_dts_init()