4  * SPDX-License-Identifier: Apache-2.0
9  * - iflag determine pending interrupt.
10  * - interrupt map decides interrupt number if implemented.
11  * - logic or/and/xor registers used when possible
33 	struct k_spinlock lock;  member
45 	const struct cfg *cfg = dev->config;  in pin_configure()
46 	struct data *data = dev->data;  in pin_configure()
47 	volatile struct grgpio_regs *regs = cfg->regs;  in pin_configure()
51 		return -ENOTSUP;  in pin_configure()
55 		return -ENOTSUP;  in pin_configure()
59 		return -ENOTSUP;  in pin_configure()
63 		return -ENOTSUP;  in pin_configure()
71 		 * lock so it serializes.  in pin_configure()
73 		key = k_spin_lock(&data->lock);  in pin_configure()
75 			regs->output_or = mask;  in pin_configure()
77 			regs->output_and = ~mask;  in pin_configure()
79 		regs->dir_or = mask;  in pin_configure()
80 		k_spin_unlock(&data->lock, key);  in pin_configure()
82 		regs->dir_and = ~mask;  in pin_configure()
90 	const struct cfg *cfg = dev->config;  in port_get_raw()
92 	*value = cfg->regs->data;  in port_get_raw()
100 	const struct cfg *cfg = dev->config;  in port_set_masked_raw()
101 	struct data *data = dev->data;  in port_set_masked_raw()
102 	volatile struct grgpio_regs *regs = cfg->regs;  in port_set_masked_raw()
107 	key = k_spin_lock(&data->lock);  in port_set_masked_raw()
108 	port_val = (regs->output & ~mask) | value;  in port_set_masked_raw()
109 	regs->output = port_val;  in port_set_masked_raw()
110 	k_spin_unlock(&data->lock, key);  in port_set_masked_raw()
117 	const struct cfg *cfg = dev->config;  in port_set_bits_raw()
118 	volatile struct grgpio_regs *regs = cfg->regs;  in port_set_bits_raw()
120 	regs->output_or = pins;  in port_set_bits_raw()
126 	const struct cfg *cfg = dev->config;  in port_clear_bits_raw()
127 	volatile struct grgpio_regs *regs = cfg->regs;  in port_clear_bits_raw()
129 	regs->output_and = ~pins;  in port_clear_bits_raw()
135 	const struct cfg *cfg = dev->config;  in port_toggle_bits()
136 	volatile struct grgpio_regs *regs = cfg->regs;  in port_toggle_bits()
138 	regs->output_xor = pins;  in port_toggle_bits()
144 	const struct cfg *cfg = dev->config;  in get_pending_int()
145 	volatile struct grgpio_regs *regs = cfg->regs;  in get_pending_int()
147 	return regs->iflag;  in get_pending_int()
152 					      enum gpio_int_mode mode,  in pin_interrupt_configure()  argument
155 	const struct cfg *cfg = dev->config;  in pin_interrupt_configure()
156 	struct data *data = dev->data;  in pin_interrupt_configure()
157 	volatile struct grgpio_regs *regs = cfg->regs;  in pin_interrupt_configure()
163 	if ((mask & data->imask) == 0) {  in pin_interrupt_configure()
165 		return -ENOTSUP;  in pin_interrupt_configure()
167 	if (mode != GPIO_INT_MODE_DISABLED) {  in pin_interrupt_configure()
173 			return -ENOTSUP;  in pin_interrupt_configure()
176 	key = k_spin_lock(&data->lock);  in pin_interrupt_configure()
177 	if (mode == GPIO_INT_MODE_DISABLED) {  in pin_interrupt_configure()
178 		regs->imask_and = ~mask;  in pin_interrupt_configure()
179 	} else if (mode == GPIO_INT_MODE_LEVEL) {  in pin_interrupt_configure()
180 		regs->imask_and = ~mask;  in pin_interrupt_configure()
181 		regs->iedge &= ~mask;  in pin_interrupt_configure()
182 		regs->ipol = (regs->ipol & ~mask) | polmask;  in pin_interrupt_configure()
183 		regs->imask_or = mask;  in pin_interrupt_configure()
184 	} else if (mode == GPIO_INT_MODE_EDGE) {  in pin_interrupt_configure()
185 		regs->imask_and = ~mask;  in pin_interrupt_configure()
186 		regs->iedge |= mask;  in pin_interrupt_configure()
187 		regs->ipol = (regs->ipol & ~mask) | polmask;  in pin_interrupt_configure()
188 		regs->imask_or = mask;  in pin_interrupt_configure()
190 		ret = -ENOTSUP;  in pin_interrupt_configure()
192 	k_spin_unlock(&data->lock, key);  in pin_interrupt_configure()
195 	regs->iflag = mask;  in pin_interrupt_configure()
197 	int interrupt = cfg->interrupt;  in pin_interrupt_configure()
198 	const int irqgen = data->irqgen;  in pin_interrupt_configure()
206 		uint32_t val = regs->irqmap[pin/4];  in pin_interrupt_configure()
208 		val >>= (3 - pin % 4) * 8;  in pin_interrupt_configure()
212 	if (interrupt && ((1 << interrupt) & data->connected) == 0) {  in pin_interrupt_configure()
221 		data->connected |= 1 << interrupt;  in pin_interrupt_configure()
231 	struct data *data = dev->data;  in manage_callback()
233 	return gpio_manage_callback(&data->cb, callback, set);  in manage_callback()
238 	const struct cfg *cfg = dev->config;  in grgpio_isr()
239 	struct data *data = dev->data;  in grgpio_isr()
240 	volatile struct grgpio_regs *regs = cfg->regs;  in grgpio_isr()
244 	pins = regs->iflag;  in grgpio_isr()
248 	regs->iflag = pins;  in grgpio_isr()
249 	gpio_fire_callbacks(&data->cb, dev, pins);  in grgpio_isr()
254 	const struct cfg *cfg = dev->config;  in grgpio_init()
255 	struct data *data = dev->data;  in grgpio_init()
256 	volatile struct grgpio_regs *regs = cfg->regs;  in grgpio_init()
258 	data->irqgen = (regs->cap & GRGPIO_CAP_IRQGEN) >> GRGPIO_CAP_IRQGEN_BIT;  in grgpio_init()
259 	regs->dir = 0;  in grgpio_init()
261 	regs->imask = 0;  in grgpio_init()
263 	regs->ipol = 0xffffffff;  in grgpio_init()
264 	regs->iedge = 0xffffffff;  in grgpio_init()
265 	regs->iflag = 0xffffffff;  in grgpio_init()
267 	data->imask = regs->ipol;  in grgpio_init()