Lines Matching full:inst
30 #define FPGA_ICE40_CONFIG_DEFINE(inst, derived_config_) \ argument
31 BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) >= FPGA_ICE40_SPI_HZ_MIN); \
32 BUILD_ASSERT(DT_INST_PROP(inst, spi_max_frequency) <= FPGA_ICE40_SPI_HZ_MAX); \
33 BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) >= FPGA_ICE40_CONFIG_DELAY_US_MIN); \
34 BUILD_ASSERT(DT_INST_PROP(inst, config_delay_us) <= UINT16_MAX); \
35 BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) >= FPGA_ICE40_CRESET_DELAY_US_MIN); \
36 BUILD_ASSERT(DT_INST_PROP(inst, creset_delay_us) <= UINT16_MAX); \
37 BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) >= FPGA_ICE40_LEADING_CLOCKS_MIN); \
38 BUILD_ASSERT(DT_INST_PROP(inst, leading_clocks) <= UINT8_MAX); \
39 BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) >= FPGA_ICE40_TRAILING_CLOCKS_MIN); \
40 BUILD_ASSERT(DT_INST_PROP(inst, trailing_clocks) <= UINT8_MAX); \
42 static const struct fpga_ice40_config fpga_ice40_config_##inst = { \
43 .bus = SPI_DT_SPEC_INST_GET(inst, \
47 .creset = GPIO_DT_SPEC_INST_GET(inst, creset_gpios), \
48 .cdone = GPIO_DT_SPEC_INST_GET(inst, cdone_gpios), \
49 .config_delay_us = DT_INST_PROP(inst, config_delay_us), \
50 .creset_delay_us = DT_INST_PROP(inst, creset_delay_us), \
51 .leading_clocks = DT_INST_PROP(inst, leading_clocks), \
52 .trailing_clocks = DT_INST_PROP(inst, trailing_clocks), \