22  * Note: When loading a bitstream, the iCE40 has a 'quirk' in that the CS
25  * CS polarity is normal (active low). Zephyr's SPI driver model currently
28  * The logical alternative would be to put the CS into GPIO mode, perform 3
29  * separate SPI transfers (inverting CS polarity as necessary) and then
82 				     volatile gpio_port_pins_t *clear, gpio_port_pins_t cs,  in fpga_ice40_spi_send_data()  argument
89 	*clear |= cs;  in fpga_ice40_spi_send_data()
113 	*set |= cs;  in fpga_ice40_spi_send_data()
126 	gpio_port_pins_t cs;  in fpga_ice40_load()  local
146 	cs = BIT(config->bus.config.cs.gpio.pin);  in fpga_ice40_load()
167 	      gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH) ||  in fpga_ice40_load()
174 	*config_bitbang->clear |= (creset | cs);  in fpga_ice40_load()
193 	*config_bitbang->set |= cs;  in fpga_ice40_load()
203 				 config_bitbang->clear, cs, clk, pico, (uint8_t *)image_ptr,  in fpga_ice40_load()
228 	(void)gpio_pin_configure_dt(&config->bus.config.cs.gpio, GPIO_OUTPUT_HIGH);  in fpga_ice40_load()