4  * SPDX-License-Identifier: Apache-2.0
15 	CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_ON;  in eos_s3_fpga_enable_clk()
16 	CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_ON;  in eos_s3_fpga_enable_clk()
17 	CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_ON | C09_CLK_GATE_PATH_2_ON;  in eos_s3_fpga_enable_clk()
18 	CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_1_ON;  in eos_s3_fpga_enable_clk()
23 	CRU->C16_CLK_GATE = C16_CLK_GATE_PATH_0_OFF;  in eos_s3_fpga_disable_clk()
24 	CRU->C21_CLK_GATE = C21_CLK_GATE_PATH_0_OFF;  in eos_s3_fpga_disable_clk()
25 	CRU->C09_CLK_GATE = C09_CLK_GATE_PATH_1_OFF | C09_CLK_GATE_PATH_2_OFF;  in eos_s3_fpga_disable_clk()
26 	CRU->C02_CLK_GATE = C02_CLK_GATE_PATH_1_OFF;  in eos_s3_fpga_disable_clk()
37 	if (PMU->FB_STATUS == FPGA_STATUS_ACTIVE) {  in eos_s3_fpga_get_status()
46 	struct quickfeather_fpga_data *data = dev->data;  in eos_s3_fpga_get_info()
48 	return data->FPGA_info;  in eos_s3_fpga_get_info()
58 	PMU->FFE_FB_PF_SW_WU = PMU_FFE_FB_PF_SW_WU_FB_WU;  in eos_s3_fpga_on()
59 	while (PMU->FFE_FB_PF_SW_WU == PMU_FFE_FB_PF_SW_WU_FB_WU) {  in eos_s3_fpga_on()
65 	/* enable FPGA programming */  in eos_s3_fpga_on()
66 	PMU->GEN_PURPOSE_0 = FB_CFG_ENABLE;  in eos_s3_fpga_on()
67 	PIF->CFG_CTL = CFG_CTL_LOAD_ENABLE;  in eos_s3_fpga_on()
78 	PMU->FB_PWR_MODE_CFG = PMU_FB_PWR_MODE_CFG_FB_SD;  in eos_s3_fpga_off()
79 	PMU->FFE_FB_PF_SW_PD = PMU_FFE_FB_PF_SW_PD_FB_PD;  in eos_s3_fpga_off()
95 		return -EAGAIN;  in eos_s3_fpga_reset()
104 		return -EINVAL;  in eos_s3_fpga_load()
110 		PIF->CFG_DATA = *bitstream;  in eos_s3_fpga_load()
114 	/* disable FPGA programming */  in eos_s3_fpga_load()
115 	PMU->GEN_PURPOSE_0 = FB_CFG_DISABLE;  in eos_s3_fpga_load()
116 	PIF->CFG_CTL = CFG_CTL_LOAD_DISABLE;  in eos_s3_fpga_load()
117 	PMU->FB_ISOLATION = FB_ISOLATION_DISABLE;  in eos_s3_fpga_load()
120 	CRU->FB_SW_RESET &= ~(FB_C21_DOMAIN_SW_RESET  in eos_s3_fpga_load()
130 	IO_MUX->PAD_19_CTRL = PAD_ENABLE;  in eos_s3_fpga_init()
132 	struct quickfeather_fpga_data *data = dev->data;  in eos_s3_fpga_init()
134 	data->FPGA_info = FPGA_INFO;  in eos_s3_fpga_init()