Lines Matching +full:0 +full:xb9
15 #define SPI_NOR_WIP_BIT BIT(0) /* Write in progress */
19 #define SPI_NOR_CMD_WRSR 0x01 /* Write status register */
20 #define SPI_NOR_CMD_RDSR 0x05 /* Read status register */
21 #define SPI_NOR_CMD_WRSR2 0x31 /* Write status register 2 */
22 #define SPI_NOR_CMD_RDSR2 0x35 /* Read status register 2 */
23 #define SPI_NOR_CMD_RDSR3 0x15 /* Read status register 3 */
24 #define SPI_NOR_CMD_WRSR3 0x11 /* Write status register 3 */
25 #define SPI_NOR_CMD_READ 0x03 /* Read data */
26 #define SPI_NOR_CMD_READ_FAST 0x0B /* Read data */
27 #define SPI_NOR_CMD_DREAD 0x3B /* Read data (1-1-2) */
28 #define SPI_NOR_CMD_2READ 0xBB /* Read data (1-2-2) */
29 #define SPI_NOR_CMD_QREAD 0x6B /* Read data (1-1-4) */
30 #define SPI_NOR_CMD_4READ 0xEB /* Read data (1-4-4) */
31 #define SPI_NOR_CMD_WREN 0x06 /* Write enable */
32 #define SPI_NOR_CMD_WRDI 0x04 /* Write disable */
33 #define SPI_NOR_CMD_PP 0x02 /* Page program */
34 #define SPI_NOR_CMD_PP_1_1_2 0xA2 /* Dual Page program (1-1-2) */
35 #define SPI_NOR_CMD_PP_1_1_4 0x32 /* Quad Page program (1-1-4) */
36 #define SPI_NOR_CMD_PP_1_4_4 0x38 /* Quad Page program (1-4-4) */
37 #define SPI_NOR_CMD_RDCR 0x15 /* Read control register */
38 #define SPI_NOR_CMD_SE 0x20 /* Sector erase */
39 #define SPI_NOR_CMD_SE_4B 0x21 /* Sector erase 4 byte address*/
40 #define SPI_NOR_CMD_BE_32K 0x52 /* Block erase 32KB */
41 #define SPI_NOR_CMD_BE 0xD8 /* Block erase */
42 #define SPI_NOR_CMD_BE_4B 0xDC /* Block erase 4 byte address*/
43 #define SPI_NOR_CMD_CE 0xC7 /* Chip erase */
44 #define SPI_NOR_CMD_RDID 0x9F /* Read JEDEC ID */
45 #define SPI_NOR_CMD_ULBPR 0x98 /* Global Block Protection Unlock */
46 #define SPI_NOR_CMD_4BA 0xB7 /* Enter 4-Byte Address Mode */
47 #define SPI_NOR_CMD_DPD 0xB9 /* Deep Power Down */
48 #define SPI_NOR_CMD_RDPD 0xAB /* Release from Deep Power Down */
49 #define SPI_NOR_CMD_WR_CFGREG2 0x72 /* Write config register 2 */
50 #define SPI_NOR_CMD_RD_CFGREG2 0x71 /* Read config register 2 */
51 #define SPI_NOR_CMD_RESET_EN 0x66 /* Reset Enable */
52 #define SPI_NOR_CMD_RESET_MEM 0x99 /* Reset Memory */
53 #define SPI_NOR_CMD_BULKE 0x60 /* Bulk Erase */
54 #define SPI_NOR_CMD_READ_4B 0x13 /* Read data 4 Byte Address */
55 #define SPI_NOR_CMD_READ_FAST_4B 0x0C /* Fast Read 4 Byte Address */
56 #define SPI_NOR_CMD_DREAD_4B 0x3C /* Read data (1-1-2) 4 Byte Address */
57 #define SPI_NOR_CMD_2READ_4B 0xBC /* Read data (1-2-2) 4 Byte Address */
58 #define SPI_NOR_CMD_QREAD_4B 0x6C /* Read data (1-1-4) 4 Byte Address */
59 #define SPI_NOR_CMD_4READ_4B 0xEC /* Read data (1-4-4) 4 Byte Address */
60 #define SPI_NOR_CMD_PP_4B 0x12 /* Page Program 4 Byte Address */
61 #define SPI_NOR_CMD_PP_1_1_4_4B 0x34 /* Quad Page program (1-1-4) 4 Byte Address */
62 #define SPI_NOR_CMD_PP_1_4_4_4B 0x3e /* Quad Page program (1-4-4) 4 Byte Address */
65 #define SPI_NOR_OCMD_SE 0x21DE /* Octal Sector erase */
66 #define SPI_NOR_OCMD_CE 0xC738 /* Octal Chip erase */
67 #define SPI_NOR_OCMD_RDSR 0x05FA /* Octal Read status register */
68 #define SPI_NOR_OCMD_DTR_RD 0xEE11 /* Octal IO DTR read command */
69 #define SPI_NOR_OCMD_RD 0xEC13 /* Octal IO read command */
70 #define SPI_NOR_OCMD_PAGE_PRG 0x12ED /* Octal Page Prog */
71 #define SPI_NOR_OCMD_WREN 0x06F9 /* Octal Write enable */
72 #define SPI_NOR_OCMD_NOP 0x00FF /* Octal No operation */
73 #define SPI_NOR_OCMD_RESET_EN 0x6699 /* Octal Reset Enable */
74 #define SPI_NOR_OCMD_RESET_MEM 0x9966 /* Octal Reset Memory */
75 #define SPI_NOR_OCMD_WR_CFGREG2 0x728D /* Octal Write configuration Register2 */
76 #define SPI_NOR_OCMD_RD_CFGREG2 0x718E /* Octal Read configuration Register2 */
77 #define SPI_NOR_OCMD_BULKE 0x609F /* Octa Bulk Erase */
80 #define SPI_NOR_PAGE_SIZE 0x0100U
81 #define SPI_NOR_SECTOR_SIZE 0x1000U
82 #define SPI_NOR_BLOCK_SIZE 0x10000U
85 #define SPI_NOR_WREN_MATCH 0x02
86 #define SPI_NOR_WREN_MASK 0x02
88 #define SPI_NOR_WEL_MATCH 0x00
89 #define SPI_NOR_WEL_MASK 0x02
91 #define SPI_NOR_MEM_RDY_MATCH 0x00
92 #define SPI_NOR_MEM_RDY_MASK 0x01
94 #define SPI_NOR_AUTO_POLLING_INTERVAL 0x10
105 #define SPI_NOR_REG2_ADDR1 0x0000000
106 #define SPI_NOR_CR2_STR_OPI_EN 0x01
107 #define SPI_NOR_CR2_DTR_OPI_EN 0x02
108 #define SPI_NOR_REG2_ADDR3 0x00000300
109 #define SPI_NOR_CR2_DUMMY_CYCLES_66MHZ 0x07
112 #define SPI_NOR_IS_ALIGNED(_ofs, _bits) (((_ofs) & BIT_MASK(_bits)) == 0)
117 #define CMD_RDCR 0x15 /* Read the configuration register. */