2  * Copyright (c) 2019-2024, Nordic Semiconductor ASA
4  * SPDX-License-Identifier: Apache-2.0
36 	/* A counter to control QSPI deactivation. */
39 	/* A flag that signals completed transfer when threads are
63 /* instance 0 flash size in bytes */
64 #if DT_INST_NODE_HAS_PROP(0, size_in_bytes)
65 #define INST_0_BYTES (DT_INST_PROP(0, size_in_bytes))
66 #elif DT_INST_NODE_HAS_PROP(0, size)
67 #define INST_0_BYTES (DT_INST_PROP(0, size) / 8)
69 #error "No size specified. 'size' or 'size-in-bytes' must be set"
72 BUILD_ASSERT(!(DT_INST_NODE_HAS_PROP(0, size_in_bytes) && DT_INST_NODE_HAS_PROP(0, size)),
73 	     "Node " DT_NODE_PATH(DT_DRV_INST(0)) " has both size and size-in-bytes "
77 #define INST_0_SCK_FREQUENCY DT_INST_PROP(0, sck_frequency)
80  * frequencies 2 - 32 MHz and the nRF53 one supports 6 - 96 MHz.
86  * Determine a configuration value (INST_0_SCK_CFG) and, if needed, a divider
94  * only be used when the QSPI peripheral is idle. When a QSPI operation is
108 				     INST_0_SCK_FREQUENCY) - 1)
121 				     INST_0_SCK_FREQUENCY) - 1)
126  * starts. It was measured with a logic analyzer (unfortunately, the nRF5340
140 					 INST_0_SCK_FREQUENCY) - 1)
146 /* 0 for MODE0 (CPOL=0, CPHA=0), 1 for MODE3 (CPOL=1, CPHA=1). */
147 #define INST_0_SPI_MODE DT_INST_PROP(0, cpol)
148 BUILD_ASSERT(DT_INST_PROP(0, cpol) == DT_INST_PROP(0, cpha),
152 #define QSPI_NODE DT_INST_BUS(0)
157 			   DT_STRING_TOKEN(DT_DRV_INST(0), \
178 … "Driver only supports NONE, S1B6, S2B1v1, S2B1v4, S2B1v5 or S2B1v6 for quad-enable-requirements");
180 #define INST_0_4BA DT_INST_PROP_OR(0, enter_4byte_addr, 0)
181 #if (INST_0_4BA != 0)
182 BUILD_ASSERT(((INST_0_4BA & 0x03) != 0),
183 	     "Driver only supports command (0xB7) for entering 4 byte addressing mode");
184 BUILD_ASSERT(DT_INST_PROP(0, address_size_32),
197  * @param buf is a valid pointer to a data buffer.
200  * If no data to transmit/receive - pass 0.
211  * @param op_code is a command value (i.e 0x9F - get Jedec ID)
229 #define QSPI_IS_SECTOR_ALIGNED(_ofs) (((_ofs) & (QSPI_SECTOR_SIZE - 1U)) == 0)
230 #define QSPI_IS_BLOCK_ALIGNED(_ofs) (((_ofs) & (QSPI_BLOCK_SIZE - 1U)) == 0)
239 		return 0;  in qspi_get_zephyr_ret_code()
242 		return -EINVAL;  in qspi_get_zephyr_ret_code()
244 		return -ECANCELED;  in qspi_get_zephyr_ret_code()
249 		return -ECANCELED;  in qspi_get_zephyr_ret_code()
254 		return -EBUSY;  in qspi_get_zephyr_ret_code()
261 	struct qspi_nor_data *dev_data = dev->data;  in qspi_lock()
263 	k_sem_take(&dev_data->sem, K_FOREVER);  in qspi_lock()
270 	struct qspi_nor_data *dev_data = dev->data;  in qspi_unlock()
272 	k_sem_give(&dev_data->sem);  in qspi_unlock()
280 	 * before a QSPI transfer is performed.  in qspi_clock_div_change()
299 	struct qspi_nor_data *dev_data = dev->data;  in qspi_acquire()
303 	if (rc < 0) {  in qspi_acquire()
309 	 * only at the last call (usage_count == 0).  in qspi_acquire()
311 	atomic_inc(&dev_data->usage_count);  in qspi_acquire()
316 	if (!dev_data->xip_enabled) {  in qspi_acquire()
325 	struct qspi_nor_data *dev_data = dev->data;  in qspi_release()
331 	deactivate = atomic_dec(&dev_data->usage_count) == 1;  in qspi_release()
334 	if (!dev_data->xip_enabled) {  in qspi_release()
347 	if (rc < 0) {  in qspi_release()
355 	struct qspi_nor_data *dev_data = dev->data;  in qspi_wait_for_completion()
359 		k_sem_take(&dev_data->sync, K_FOREVER);  in qspi_wait_for_completion()
363 		while (!dev_data->ready) {  in qspi_wait_for_completion()
367 		dev_data->ready = false;  in qspi_wait_for_completion()
376 	k_sem_give(&dev_data->sync);  in qspi_complete()
378 	dev_data->ready = true;  in qspi_complete()
408 		return -EINVAL;  in qspi_send_cmd()
412 	size_t tx_len = 0;  in qspi_send_cmd()
414 	size_t rx_len = 0;  in qspi_send_cmd()
415 	size_t xfer_len = sizeof(cmd->op_code);  in qspi_send_cmd()
417 	if (cmd->tx_buf) {  in qspi_send_cmd()
418 		tx_buf = cmd->tx_buf->buf;  in qspi_send_cmd()
419 		tx_len = cmd->tx_buf->len;  in qspi_send_cmd()
422 	if (cmd->rx_buf) {  in qspi_send_cmd()
423 		rx_buf = cmd->rx_buf->buf;  in qspi_send_cmd()
424 		rx_len = cmd->rx_buf->len;  in qspi_send_cmd()
427 	if ((rx_len != 0) && (tx_len != 0)) {  in qspi_send_cmd()
429 			return -EINVAL;  in qspi_send_cmd()
440 			cmd->op_code, xfer_len);  in qspi_send_cmd()
441 		return -EINVAL;  in qspi_send_cmd()
445 		.opcode = cmd->op_code,  in qspi_send_cmd()
464 	if (sr_num > 2 || sr_num == 0) {  in qspi_rdsr()
465 		return -EINVAL;  in qspi_rdsr()
470 	uint8_t sr = 0xFF;  in qspi_rdsr()
481 	return (rc < 0) ? rc : sr;  in qspi_rdsr()
496 	} while ((rc >= 0)  in qspi_wait_while_writing()
497 		 && ((rc & SPI_NOR_WIP_BIT) != 0U));  in qspi_wait_while_writing()
499 	return (rc < 0) ? rc : 0;  in qspi_wait_while_writing()
504 	int rc = 0;  in qspi_wrsr()
507 	uint8_t sr_array[2] = {0};  in qspi_wrsr()
509 	if (sr_num > 2 || sr_num == 0) {  in qspi_wrsr()
510 		return -EINVAL;  in qspi_wrsr()
514 		sr_array[0] = sr_val;  in qspi_wrsr()
518 		if (rc < 0) {  in qspi_wrsr()
533 		if (rc < 0) {  in qspi_wrsr()
537 		sr_array[0] = rc;  in qspi_wrsr()
540 		/* Writing sr2 uses a dedicated WRSR2 command */  in qspi_wrsr()
541 		sr_array[0] = sr_val;  in qspi_wrsr()
545 		return -EINVAL;  in qspi_wrsr()
564 	if (rc == 0) {  in qspi_wrsr()
575 	const struct qspi_nor_config *params = dev->config;  in qspi_erase()
579 	if (rc != 0) {  in qspi_erase()
582 	while (size > 0) {  in qspi_erase()
584 		uint32_t adj = 0;  in qspi_erase()
586 		if (size == params->size) {  in qspi_erase()
597 			/* 4kB sector erase */  in qspi_erase()
601 			/* minimal erase size is at least a sector size */  in qspi_erase()
602 			LOG_ERR("unsupported at 0x%lx size %zu", (long)addr, size);  in qspi_erase()
609 			size -= adj;  in qspi_erase()
611 			/* Erasing flash pages takes a significant period of time and the  in qspi_erase()
616 			if (rc < 0) {  in qspi_erase()
617 				LOG_ERR("wait error at 0x%lx size %zu", (long)addr, size);  in qspi_erase()
621 			LOG_ERR("erase error at 0x%lx size %zu", (long)addr, size);  in qspi_erase()
629 	return rc != 0 ? rc : rc2;  in qspi_erase()
634 	const struct qspi_nor_config *dev_config = dev->config;  in configure_chip()
635 	int rc = 0;  in configure_chip()
646 			&dev_config->nrfx_cfg.prot_if;  in configure_chip()
647 		bool qe_value = (prot_if->writeoc == NRF_QSPI_WRITEOC_PP4IO) ||  in configure_chip()
648 				(prot_if->writeoc == NRF_QSPI_WRITEOC_PP4O)  ||  in configure_chip()
649 				(prot_if->readoc == NRF_QSPI_READOC_READ4IO) ||  in configure_chip()
650 				(prot_if->readoc == NRF_QSPI_READOC_READ4O)  ||  in configure_chip()
651 				(prot_if->readoc == NRF_QSPI_READOC_READ2IO);  in configure_chip()
652 		uint8_t sr_num = 0;  in configure_chip()
653 		uint8_t qe_mask = 0;  in configure_chip()
663 		return -EINVAL;  in configure_chip()
667 		if (rc < 0) {  in configure_chip()
673 		bool qe_state = ((sr & qe_mask) != 0U);  in configure_chip()
676 			(qe_state != qe_value) ? "updating" : "no-change");  in configure_chip()
678 		rc = 0;  in configure_chip()
684 		if (rc < 0) {  in configure_chip()
691 	if (INST_0_4BA != 0) {  in configure_chip()
699 		rc = qspi_send_cmd(dev, &cmd, (INST_0_4BA & 0x02));  in configure_chip()
701 		if (rc < 0) {  in configure_chip()
749 		0,		/* wait state */  in qspi_sfdp_read()
794 	off_t flash_prefix = (WORD_SIZE - (addr % WORD_SIZE)) % WORD_SIZE;  in read_non_aligned()
800 	off_t dest_prefix = (WORD_SIZE - (off_t)dptr % WORD_SIZE) % WORD_SIZE;  in read_non_aligned()
806 	off_t flash_suffix = (size - flash_prefix) % WORD_SIZE;  in read_non_aligned()
807 	off_t flash_middle = size - flash_prefix - flash_suffix;  in read_non_aligned()
808 	off_t dest_middle = size - dest_prefix -  in read_non_aligned()
809 			    (size - dest_prefix) % WORD_SIZE;  in read_non_aligned()
813 		flash_suffix = size - flash_prefix - flash_middle;  in read_non_aligned()
819 	if (flash_middle != 0) {  in read_non_aligned()
834 	if (flash_prefix != 0) {  in read_non_aligned()
835 		res = nrfx_qspi_read(buf, WORD_SIZE, addr -  in read_non_aligned()
836 				     (WORD_SIZE - flash_prefix));  in read_non_aligned()
841 		memcpy(dptr, buf + WORD_SIZE - flash_prefix, flash_prefix);  in read_non_aligned()
845 	if (flash_suffix != 0) {  in read_non_aligned()
861 	const struct qspi_nor_config *params = dev->config;  in qspi_nor_read()
865 		return -EINVAL;  in qspi_nor_read()
868 	/* read size must be non-zero */  in qspi_nor_read()
870 		return 0;  in qspi_nor_read()
874 	if (addr < 0 ||  in qspi_nor_read()
875 	    (addr + size) > params->size) {  in qspi_nor_read()
878 			"Addr: 0x%lx size %zu", (long)addr, size);  in qspi_nor_read()
879 		return -EINVAL;  in qspi_nor_read()
913 BUILD_ASSERT((CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE % 4) == 0,
916 /* If enabled write using a stack-allocated aligned SRAM buffer as
926 	if (CONFIG_NORDIC_QSPI_NOR_STACK_WRITE_BUFFER_SIZE > 0) {  in write_through_buffer()
930 		while ((slen > 0) && (res == NRFX_SUCCESS)) {  in write_through_buffer()
938 				slen -= len;  in write_through_buffer()
953 	const struct qspi_nor_config *params = dev->config;  in qspi_nor_write()
957 		return -EINVAL;  in qspi_nor_write()
960 	/* write size must be non-zero, less than 4, or a multiple of 4 */  in qspi_nor_write()
961 	if ((size == 0)  in qspi_nor_write()
962 	    || ((size > 4) && ((size % 4U) != 0))) {  in qspi_nor_write()
963 		return -EINVAL;  in qspi_nor_write()
965 	/* address must be 4-byte aligned */  in qspi_nor_write()
966 	if ((addr % 4U) != 0) {  in qspi_nor_write()
967 		return -EINVAL;  in qspi_nor_write()
971 	if (addr < 0 ||  in qspi_nor_write()
972 	    (addr + size) > params->size) {  in qspi_nor_write()
975 			"Addr: 0x%lx size %zu", (long)addr, size);  in qspi_nor_write()
976 		return -EINVAL;  in qspi_nor_write()
982 	if (rc == 0) {  in qspi_nor_write()
1002 	return rc != 0 ? rc : rc2;  in qspi_nor_write()
1007 	const struct qspi_nor_config *params = dev->config;  in qspi_nor_erase()
1010 	/* address must be sector-aligned */  in qspi_nor_erase()
1011 	if ((addr % QSPI_SECTOR_SIZE) != 0) {  in qspi_nor_erase()
1012 		return -EINVAL;  in qspi_nor_erase()
1015 	/* size must be a non-zero multiple of sectors */  in qspi_nor_erase()
1016 	if ((size == 0) || (size % QSPI_SECTOR_SIZE) != 0) {  in qspi_nor_erase()
1017 		return -EINVAL;  in qspi_nor_erase()
1021 	if (addr < 0 ||  in qspi_nor_erase()
1022 	    (addr + size) > params->size) {  in qspi_nor_erase()
1025 			"Addr: 0x%lx size %zu", (long)addr, size);  in qspi_nor_erase()
1026 		return -EINVAL;  in qspi_nor_erase()
1041 	int rc = 0;  in qspi_nor_write_protection_set()
1046 	if (qspi_send_cmd(dev, &cmd, false) != 0) {  in qspi_nor_write_protection_set()
1047 		rc = -EIO;  in qspi_nor_write_protection_set()
1055 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_init()
1060 	res = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);  in qspi_init()
1062 	if (rc < 0) {  in qspi_init()
1066 #if DT_INST_NODE_HAS_PROP(0, rx_delay)  in qspi_init()
1068 		nrf_qspi_iftiming_set(NRF_QSPI, DT_INST_PROP(0, rx_delay));  in qspi_init()
1078 	 * CONFIG_PM_DEVICE set to enter DPD mode, as a previously executing image  in qspi_init()
1080 	 * bootloader) might have set DPD mode before reboot. As a result,  in qspi_init()
1084 	if (rc < 0) {  in qspi_init()
1090 	if (rc < 0) {  in qspi_init()
1094 	if (memcmp(dev_config->id, id, SPI_NOR_MAX_ID_LEN) != 0) {  in qspi_init()
1096 			id[0], id[1], id[2], dev_config->id[0],  in qspi_init()
1097 			dev_config->id[1], dev_config->id[2]);  in qspi_init()
1098 		return -ENODEV;  in qspi_init()
1107 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_nor_init()
1110 	rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);  in qspi_nor_init()
1111 	if (rc < 0) {  in qspi_nor_init()
1116 		    nrfx_isr, nrfx_qspi_irq_handler, 0);  in qspi_nor_init()
1129 	if (rc == 0) {  in qspi_nor_init()
1142 /* instance 0 page count */
1173 		.erase_value = 0xff,  in qspi_flash_get_parameters()
1185 	return 0;  in qspi_nor_get_size()
1206 	if (IS_ENABLED(DT_INST_PROP(0, has_dpd))) {  in enter_dpd()
1210 		uint32_t t_enter_dpd = DT_INST_PROP_OR(0, t_enter_dpd, 0);  in enter_dpd()
1214 		if (rc < 0) {  in enter_dpd()
1226 	return 0;  in enter_dpd()
1232 	if (IS_ENABLED(DT_INST_PROP(0, has_dpd))) {  in exit_dpd()
1245 		uint32_t t_exit_dpd = DT_INST_PROP_OR(0, t_exit_dpd, 0);  in exit_dpd()
1255 			return -EIO;  in exit_dpd()
1259 		if (rc < 0) {  in exit_dpd()
1271 	return 0;  in exit_dpd()
1277 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_suspend()
1283 		return -EBUSY;  in qspi_suspend()
1287 	if (rc < 0) {  in qspi_suspend()
1293 	return pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_SLEEP);  in qspi_suspend()
1298 	const struct qspi_nor_config *dev_config = dev->config;  in qspi_resume()
1302 	rc = pinctrl_apply_state(dev_config->pcfg, PINCTRL_STATE_DEFAULT);  in qspi_resume()
1303 	if (rc < 0) {  in qspi_resume()
1307 	res = nrfx_qspi_init(&dev_config->nrfx_cfg, qspi_handler, dev->data);  in qspi_resume()
1309 		return -EIO;  in qspi_resume()
1321 		return -EBUSY;  in qspi_nor_pm_action()
1337 		rc = -ENOTSUP;  in qspi_nor_pm_action()
1349 	struct qspi_nor_data *dev_data = dev->data;  in z_impl_nrf_qspi_nor_xip_enable()
1351 	if (dev_data->xip_enabled == enable) {  in z_impl_nrf_qspi_nor_xip_enable()
1363 	dev_data->xip_enabled = enable;  in z_impl_nrf_qspi_nor_xip_enable()
1385 	.sync = Z_SEM_INITIALIZER(qspi_nor_dev_data.sync, 0, 1),
1398 		.readoc = COND_CODE_1(DT_INST_NODE_HAS_PROP(0, readoc),
1400 				 DT_STRING_UPPER_TOKEN(DT_DRV_INST(0),
1403 		.writeoc = COND_CODE_1(DT_INST_NODE_HAS_PROP(0, writeoc),
1405 				 DT_STRING_UPPER_TOKEN(DT_DRV_INST(0),
1408 		.addrmode = DT_INST_PROP(0, address_size_32)
1414 		.sck_delay = DT_INST_PROP(0, sck_delay),
1420 	.id = DT_INST_PROP(0, jedec_id),
1423 PM_DEVICE_DT_INST_DEFINE(0, qspi_nor_pm_action);
1425 DEVICE_DT_INST_DEFINE(0, qspi_nor_init, PM_DEVICE_DT_INST_GET(0),