4  * SPDX-License-Identifier: Apache-2.0
27  * offset and len must be aligned on 8 for write,
32 			     bool write)  in flash_stm32_valid_range()  argument
46 	if (write && !flash_stm32_valid_write(offset, len)) {  in flash_stm32_valid_range()
54 	if (regs->ACR & FLASH_ACR_DCEN) {  in flush_cache()
55 		regs->ACR &= ~FLASH_ACR_DCEN;  in flush_cache()
59 		regs->ACR |= FLASH_ACR_DCRST;  in flush_cache()
60 		regs->ACR &= ~FLASH_ACR_DCRST;  in flush_cache()
61 		regs->ACR |= FLASH_ACR_DCEN;  in flush_cache()
64 	if (regs->ACR & FLASH_ACR_ICEN) {  in flush_cache()
65 		regs->ACR &= ~FLASH_ACR_ICEN;  in flush_cache()
70 		regs->ACR |= FLASH_ACR_ICRST;  in flush_cache()
71 		regs->ACR &= ~FLASH_ACR_ICRST;  in flush_cache()
72 		regs->ACR |= FLASH_ACR_ICEN;  in flush_cache()
87 	if (regs->CR & FLASH_CR_LOCK) {  in write_dword()
89 		return -EIO;  in write_dword()
100 	 * It is allowed to write only zeros over an already written dword  in write_dword()
106 		return -EIO;  in write_dword()
112 	 * "Data cache might be corrupted during Flash memory read-while-write operation"  in write_dword()
114 	if (regs->ACR & FLASH_ACR_DCEN) {  in write_dword()
116 		regs->ACR &= (~FLASH_ACR_DCEN);  in write_dword()
121 	regs->CR |= FLASH_CR_PG;  in write_dword()
123 	/* Flush the register write */  in write_dword()
124 	tmp = regs->CR;  in write_dword()
126 	/* Perform the data write operation at the desired memory address */  in write_dword()
134 	regs->CR &= (~FLASH_CR_PG);  in write_dword()
139 		regs->ACR |= FLASH_ACR_DCRST;  in write_dword()
140 		regs->ACR &= (~FLASH_ACR_DCRST);  in write_dword()
141 		regs->ACR |= FLASH_ACR_DCEN;  in write_dword()
156 	if (regs->CR & FLASH_CR_LOCK) {  in erase_page()
158 		return -EIO;  in erase_page()
174 		regs->CR &= ~FLASH_CR_BKER_Msk;  in erase_page()
179 		regs->CR &= ~FLASH_CR_BKER_Msk;  in erase_page()
180 		page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;  in erase_page()
184 		regs->CR |= FLASH_CR_BKER;  in erase_page()
189 		regs->CR |= FLASH_CR_BKER;  in erase_page()
190 		page = (offset - BANK2_OFFSET) / FLASH_PAGE_SIZE;  in erase_page()
194 		return -EINVAL;  in erase_page()
202 	regs->CR |= FLASH_CR_PER;  in erase_page()
203 	regs->CR &= ~FLASH_CR_PNB_Msk;  in erase_page()
204 	regs->CR |= (page << FLASH_CR_PNB_Pos);  in erase_page()
207 	regs->CR |= FLASH_CR_STRT;  in erase_page()
209 	/* flush the register write */  in erase_page()
210 	tmp = regs->CR;  in erase_page()
218 	regs->CR &= ~(FLASH_CR_PER | FLASH_CR_BKER);  in erase_page()
220 	regs->CR &= ~(FLASH_CR_PER);  in erase_page()
233 	for (; address <= offset + len - 1 ; address += FLASH_PAGE_SIZE) {  in flash_stm32_block_erase_loop()
264 	if (regs->CR & FLASH_CR_OPTLOCK) {  in flash_stm32_option_bytes_write()
265 		return -EIO;  in flash_stm32_option_bytes_write()
268 	if ((regs->OPTR & mask) == value) {  in flash_stm32_option_bytes_write()
277 	regs->OPTR = (regs->OPTR & ~mask) | value;  in flash_stm32_option_bytes_write()
278 	regs->CR |= FLASH_CR_OPTSTRT;  in flash_stm32_option_bytes_write()
280 	/* Make sure previous write is completed. */  in flash_stm32_option_bytes_write()
295 	return regs->OPTR;  in flash_stm32_option_bytes_read()
301  * Remark for future development implementing Write Protection for the L4 parts:
303  * STM32L4 allows for 2 write protected memory areas, c.f. FLASH_WEP1AR, FLASH_WRP1BR
308  * To implement Write Protection for L4 one should thus add a new EX_OP like
319 	return (regs->OPTR & FLASH_OPTR_RDP_Msk) >> FLASH_OPTR_RDP_Pos;  in flash_stm32_get_rdp_level()
346 					- (PAGES_PER_BANK * FLASH_PAGE_SIZE);  in flash_stm32_page_layout()
369 	if (READ_BIT(FLASH->OPTR, FLASH_STM32_DBANK) == 0U) {  in flash_stm32_check_configuration()
372 		return -ENOTSUP;  in flash_stm32_check_configuration()