Lines Matching +full:rx +full:- +full:sync +full:- +full:mode
6 * SPDX-License-Identifier: Apache-2.0
58 /* In dual-flash mode, total size is twice the size of one flash component */
110 struct k_sem sync; member
118 enum jesd216_mode_type mode; member
125 * If set addressed operations should use 32-bit rather than
126 * 24-bit addresses.
138 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_lock_thread()
140 k_sem_take(&dev_data->sem, K_FOREVER); in qspi_lock_thread()
145 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_unlock_thread()
147 k_sem_give(&dev_data->sem); in qspi_unlock_thread()
153 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_set_address_size()
155 if (dev_data->flag_access_32bit) { in qspi_set_address_size()
156 cmd->AddressSize = QSPI_ADDRESS_32_BITS; in qspi_set_address_size()
160 cmd->AddressSize = QSPI_ADDRESS_24_BITS; in qspi_set_address_size()
166 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_prepare_quad_read()
168 __ASSERT_NO_MSG(dev_data->mode == JESD216_MODE_114 || in qspi_prepare_quad_read()
169 dev_data->mode == JESD216_MODE_144); in qspi_prepare_quad_read()
171 cmd->Instruction = dev_data->qspi_read_cmd; in qspi_prepare_quad_read()
172 cmd->AddressMode = ((dev_data->mode == JESD216_MODE_114) in qspi_prepare_quad_read()
175 cmd->DataMode = QSPI_DATA_4_LINES; in qspi_prepare_quad_read()
176 cmd->DummyCycles = dev_data->qspi_read_cmd_latency; in qspi_prepare_quad_read()
184 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_prepare_quad_program()
186 __ASSERT_NO_MSG(dev_data->qspi_write_cmd == SPI_NOR_CMD_PP_1_1_4 || in qspi_prepare_quad_program()
187 dev_data->qspi_write_cmd == SPI_NOR_CMD_PP_1_4_4); in qspi_prepare_quad_program()
189 cmd->Instruction = dev_data->qspi_write_cmd; in qspi_prepare_quad_program()
191 /* Microchip qspi-NOR flash, does not follow the standard rules */ in qspi_prepare_quad_program()
192 if (cmd->Instruction == SPI_NOR_CMD_PP_1_1_4) { in qspi_prepare_quad_program()
193 cmd->AddressMode = QSPI_ADDRESS_4_LINES; in qspi_prepare_quad_program()
196 cmd->AddressMode = ((cmd->Instruction == SPI_NOR_CMD_PP_1_1_4) in qspi_prepare_quad_program()
200 cmd->DataMode = QSPI_DATA_4_LINES; in qspi_prepare_quad_program()
201 cmd->DummyCycles = 0; in qspi_prepare_quad_program()
211 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in qspi_send_cmd()
212 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_send_cmd()
217 LOG_DBG("Instruction 0x%x", cmd->Instruction); in qspi_send_cmd()
219 dev_data->cmd_status = 0; in qspi_send_cmd()
221 hal_ret = HAL_QSPI_Command_IT(&dev_data->hqspi, (QSPI_CommandTypeDef *)cmd); in qspi_send_cmd()
224 return -EIO; in qspi_send_cmd()
226 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in qspi_send_cmd()
228 k_sem_take(&dev_data->sync, K_FOREVER); in qspi_send_cmd()
230 return dev_data->cmd_status; in qspi_send_cmd()
239 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in qspi_read_access()
240 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_read_access()
245 cmd->NbData = size; in qspi_read_access()
247 dev_data->cmd_status = 0; in qspi_read_access()
249 hal_ret = HAL_QSPI_Command_IT(&dev_data->hqspi, cmd); in qspi_read_access()
252 return -EIO; in qspi_read_access()
256 hal_ret = HAL_QSPI_Receive_DMA(&dev_data->hqspi, data); in qspi_read_access()
258 hal_ret = HAL_QSPI_Receive_IT(&dev_data->hqspi, data); in qspi_read_access()
262 return -EIO; in qspi_read_access()
265 k_sem_take(&dev_data->sync, K_FOREVER); in qspi_read_access()
267 return dev_data->cmd_status; in qspi_read_access()
276 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in qspi_write_access()
277 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_write_access()
282 LOG_DBG("Instruction 0x%x", cmd->Instruction); in qspi_write_access()
284 cmd->NbData = size; in qspi_write_access()
286 dev_data->cmd_status = 0; in qspi_write_access()
288 hal_ret = HAL_QSPI_Command_IT(&dev_data->hqspi, cmd); in qspi_write_access()
291 return -EIO; in qspi_write_access()
295 hal_ret = HAL_QSPI_Transmit_DMA(&dev_data->hqspi, (uint8_t *)data); in qspi_write_access()
297 hal_ret = HAL_QSPI_Transmit_IT(&dev_data->hqspi, (uint8_t *)data); in qspi_write_access()
301 return -EIO; in qspi_write_access()
303 LOG_DBG("CCR 0x%x", dev_cfg->regs->CCR); in qspi_write_access()
305 k_sem_take(&dev_data->sync, K_FOREVER); in qspi_write_access()
307 return dev_data->cmd_status; in qspi_write_access()
314 * and compare to the jedec-id from the DTYS table exists
318 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_read_jedec_id()
333 hal_ret = HAL_QSPI_Command_IT(&dev_data->hqspi, &cmd); in qspi_read_jedec_id()
337 return -EIO; in qspi_read_jedec_id()
340 hal_ret = HAL_QSPI_Receive(&dev_data->hqspi, data, HAL_QSPI_TIMEOUT_DEFAULT_VALUE); in qspi_read_jedec_id()
343 return -EIO; in qspi_read_jedec_id()
346 LOG_DBG("Read JESD216-ID"); in qspi_read_jedec_id()
348 dev_data->cmd_status = 0; in qspi_read_jedec_id()
382 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_read_sfdp()
400 hal_ret = HAL_QSPI_Command(&dev_data->hqspi, &cmd, in qspi_read_sfdp()
404 return -EIO; in qspi_read_sfdp()
407 hal_ret = HAL_QSPI_Receive(&dev_data->hqspi, (uint8_t *)data, in qspi_read_sfdp()
411 return -EIO; in qspi_read_sfdp()
414 dev_data->cmd_status = 0; in qspi_read_sfdp()
422 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in qspi_address_is_valid()
423 size_t flash_size = dev_cfg->flash_size; in qspi_address_is_valid()
434 struct flash_stm32_qspi_data *dev_data = dev->data; in stm32_qspi_set_memory_mapped()
456 hal_ret = HAL_QSPI_MemoryMapped(&dev_data->hqspi, &cmd, &mem_mapped); in stm32_qspi_set_memory_mapped()
459 return -EIO; in stm32_qspi_set_memory_mapped()
462 LOG_DBG("MemoryMap mode enabled"); in stm32_qspi_set_memory_mapped()
468 struct flash_stm32_qspi_data *dev_data = dev->data; in stm32_qspi_is_memory_mapped()
470 return READ_BIT(dev_data->hqspi.Instance->CCR, QUADSPI_CCR_FMODE) == QUADSPI_CCR_FMODE; in stm32_qspi_is_memory_mapped()
475 struct flash_stm32_qspi_data *dev_data = dev->data; in stm32_qspi_abort()
478 hal_ret = HAL_QSPI_Abort(&dev_data->hqspi); in stm32_qspi_abort()
481 return -EIO; in stm32_qspi_abort()
496 return -EINVAL; in flash_stm32_qspi_read()
499 /* read non-zero size */ in flash_stm32_qspi_read()
507 /* Do reads through memory-mapping instead of indirect */ in flash_stm32_qspi_read()
520 LOG_DBG("Memory-mapped read from 0x%08lx, len %zu", mmap_addr, size); in flash_stm32_qspi_read()
579 return -EINVAL; in flash_stm32_qspi_write()
582 /* write non-zero size */ in flash_stm32_qspi_write()
609 LOG_ERR("Failed to abort memory-mapped access before write"); in flash_stm32_qspi_write()
624 if (((addr + to_write - 1U) / SPI_NOR_PAGE_SIZE) in flash_stm32_qspi_write()
626 to_write = SPI_NOR_PAGE_SIZE - in flash_stm32_qspi_write()
641 size -= to_write; in flash_stm32_qspi_write()
661 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in flash_stm32_qspi_erase()
662 struct flash_stm32_qspi_data *dev_data = dev->data; in flash_stm32_qspi_erase()
668 return -EINVAL; in flash_stm32_qspi_erase()
671 /* erase non-zero size */ in flash_stm32_qspi_erase()
690 LOG_ERR("Failed to abort memory-mapped access before erase"); in flash_stm32_qspi_erase()
700 if (size == dev_cfg->flash_size) { in flash_stm32_qspi_erase()
705 size -= dev_cfg->flash_size; in flash_stm32_qspi_erase()
708 dev_data->erase_types; in flash_stm32_qspi_erase()
716 if ((etp->exp != 0) in flash_stm32_qspi_erase()
717 && SPI_NOR_IS_ALIGNED(addr, etp->exp) in flash_stm32_qspi_erase()
718 && SPI_NOR_IS_ALIGNED(size, etp->exp) in flash_stm32_qspi_erase()
720 || (etp->exp > bet->exp))) { in flash_stm32_qspi_erase()
722 cmd_erase.Instruction = bet->cmd; in flash_stm32_qspi_erase()
727 addr += BIT(bet->exp); in flash_stm32_qspi_erase()
728 size -= BIT(bet->exp); in flash_stm32_qspi_erase()
732 ret = -EINVAL; in flash_stm32_qspi_erase()
760 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in flash_stm32_qspi_get_size()
762 *size = (uint64_t)dev_cfg->flash_size; in flash_stm32_qspi_get_size()
769 struct flash_stm32_qspi_data *dev_data = dev->data; in flash_stm32_qspi_isr()
771 HAL_QSPI_IRQHandler(&dev_data->hqspi); in flash_stm32_qspi_isr()
812 dev_data->cmd_status = -EIO; in HAL_QSPI_ErrorCallback()
814 k_sem_give(&dev_data->sync); in HAL_QSPI_ErrorCallback()
825 k_sem_give(&dev_data->sync); in HAL_QSPI_CmdCpltCallback()
829 * Rx Transfer completed callback.
836 k_sem_give(&dev_data->sync); in HAL_QSPI_RxCpltCallback()
847 k_sem_give(&dev_data->sync); in HAL_QSPI_TxCpltCallback()
858 k_sem_give(&dev_data->sync); in HAL_QSPI_StatusMatchCallback()
871 dev_data->cmd_status = -EIO; in HAL_QSPI_TimeOutCallback()
873 k_sem_give(&dev_data->sync); in HAL_QSPI_TimeOutCallback()
881 struct flash_stm32_qspi_data *dev_data = dev->data; in flash_stm32_qspi_pages_layout()
883 *layout = &dev_data->layout; in flash_stm32_qspi_pages_layout()
906 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in setup_pages_layout()
907 struct flash_stm32_qspi_data *data = dev->data; in setup_pages_layout()
908 const size_t flash_size = dev_cfg->flash_size; in setup_pages_layout()
909 uint32_t layout_page_size = data->page_size; in setup_pages_layout()
914 for (size_t i = 0; i < ARRAY_SIZE(data->erase_types); ++i) { in setup_pages_layout()
915 const struct jesd216_erase_type *etp = &data->erase_types[i]; in setup_pages_layout()
917 if ((etp->cmd != 0) in setup_pages_layout()
918 && ((exp == 0) || (etp->exp < exp))) { in setup_pages_layout()
919 exp = etp->exp; in setup_pages_layout()
924 return -ENOTSUP; in setup_pages_layout()
945 data->layout.pages_size = layout_page_size; in setup_pages_layout()
946 data->layout.pages_count = flash_size / layout_page_size; in setup_pages_layout()
947 LOG_DBG("layout %u x %u By pages", data->layout.pages_count, in setup_pages_layout()
948 data->layout.pages_size); in setup_pages_layout()
973 * No need to Read control register afterwards to verify if 4byte addressing mode in qspi_program_addr_4b()
975 * and the SPI_NOR_CMD_RDCR is vendor-specific : in qspi_program_addr_4b()
977 * Moreover bit value meaning is also vendor-specific in qspi_program_addr_4b()
1001 return -EINVAL; in qspi_read_status_register()
1009 struct flash_stm32_qspi_data *dev_data = dev->data; in qspi_write_status_register()
1026 if (dev_data->qer_type == JESD216_DW15_QER_S2B1v1) { in qspi_write_status_register()
1039 if ((dev_data->qer_type == JESD216_DW15_QER_VAL_S2B1v1) || in qspi_write_status_register()
1040 (dev_data->qer_type == JESD216_DW15_QER_VAL_S2B1v4) || in qspi_write_status_register()
1041 (dev_data->qer_type == JESD216_DW15_QER_VAL_S2B1v5)) { in qspi_write_status_register()
1056 return -EINVAL; in qspi_write_status_register()
1081 struct flash_stm32_qspi_data *data = dev->data; in qspi_program_quad_io()
1087 switch (data->qer_type) { in qspi_program_quad_io()
1110 return -ENOTSUP; in qspi_program_quad_io()
1148 return -EIO; in qspi_program_quad_io()
1158 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in spi_nor_process_bfp()
1159 struct flash_stm32_qspi_data *data = dev->data; in spi_nor_process_bfp()
1160 struct jesd216_erase_type *etp = data->erase_types; in spi_nor_process_bfp()
1165 if (flash_size != dev_cfg->flash_size) { in spi_nor_process_bfp()
1169 LOG_INF("%s: %u MiBy flash", dev->name, (uint32_t)(flash_size >> 20)); in spi_nor_process_bfp()
1174 memset(data->erase_types, 0, sizeof(data->erase_types)); in spi_nor_process_bfp()
1175 for (uint8_t ti = 1; ti <= ARRAY_SIZE(data->erase_types); ++ti) { in spi_nor_process_bfp()
1178 (uint32_t)BIT(etp->exp), etp->cmd); in spi_nor_process_bfp()
1183 data->page_size = jesd216_bfp_page_size(php, bfp); in spi_nor_process_bfp()
1185 LOG_DBG("Page size %u bytes", data->page_size); in spi_nor_process_bfp()
1197 * write enable to switch to 4 bytes addressing mode. in spi_nor_process_bfp()
1203 data->flag_access_32bit = true; in spi_nor_process_bfp()
1204 LOG_INF("Flash - address mode: 4B"); in spi_nor_process_bfp()
1206 LOG_ERR("Unable to enter 4B mode: %d\n", rc); in spi_nor_process_bfp()
1213 data->flag_access_32bit = true; in spi_nor_process_bfp()
1214 LOG_INF("Flash - address mode: 4B"); in spi_nor_process_bfp()
1218 * Only check if the 1-4-4 (i.e. 4READ) or 1-1-4 (QREAD) in spi_nor_process_bfp()
1219 * is supported - other modes are not. in spi_nor_process_bfp()
1227 /* reset active mode */ in spi_nor_process_bfp()
1228 data->mode = STM32_QSPI_UNKNOWN_MODE; in spi_nor_process_bfp()
1234 LOG_INF("Quad read mode %d instr [0x%x] supported", in spi_nor_process_bfp()
1237 data->mode = supported_modes[i]; in spi_nor_process_bfp()
1238 data->qspi_read_cmd = res.instr; in spi_nor_process_bfp()
1239 data->qspi_read_cmd_latency = res.wait_states; in spi_nor_process_bfp()
1242 data->qspi_read_cmd_latency += res.mode_clocks; in spi_nor_process_bfp()
1247 /* don't continue when there is no supported mode */ in spi_nor_process_bfp()
1248 if (data->mode == STM32_QSPI_UNKNOWN_MODE) { in spi_nor_process_bfp()
1249 LOG_ERR("No supported flash read mode found"); in spi_nor_process_bfp()
1250 return -ENOTSUP; in spi_nor_process_bfp()
1253 LOG_INF("Quad read mode %d instr [0x%x] will be used", data->mode, res.instr); in spi_nor_process_bfp()
1262 data->qer_type = dw15.qer; in spi_nor_process_bfp()
1265 LOG_INF("QE requirement mode: %x", data->qer_type); in spi_nor_process_bfp()
1270 LOG_ERR("Failed to enable Quad mode: %d", rc); in spi_nor_process_bfp()
1274 LOG_INF("Quad mode enabled"); in spi_nor_process_bfp()
1283 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in flash_stm32_qspi_gpio_reset()
1286 gpio_pin_configure_dt(&dev_cfg->reset, GPIO_OUTPUT_ACTIVE); in flash_stm32_qspi_gpio_reset()
1288 gpio_pin_set_dt(&dev_cfg->reset, 0); in flash_stm32_qspi_gpio_reset()
1322 const struct flash_stm32_qspi_config *dev_cfg = dev->config; in flash_stm32_qspi_init()
1323 struct flash_stm32_qspi_data *dev_data = dev->data; in flash_stm32_qspi_init()
1329 ret = pinctrl_apply_state(dev_cfg->pcfg, PINCTRL_STATE_DEFAULT); in flash_stm32_qspi_init()
1347 struct dma_config dma_cfg = dev_data->dma.cfg; in flash_stm32_qspi_init()
1350 if (!device_is_ready(dev_data->dma.dev)) { in flash_stm32_qspi_init()
1351 LOG_ERR("%s device not ready", dev_data->dma.dev->name); in flash_stm32_qspi_init()
1352 return -ENODEV; in flash_stm32_qspi_init()
1359 ret = dma_config(dev_data->dma.dev, dev_data->dma.channel, &dma_cfg); in flash_stm32_qspi_init()
1367 return -EINVAL; in flash_stm32_qspi_init()
1370 int index = find_lsb_set(dma_cfg.source_data_size) - 1; in flash_stm32_qspi_init()
1376 hdma.Init.Mode = DMA_NORMAL; in flash_stm32_qspi_init()
1381 hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg, in flash_stm32_qspi_init()
1382 dev_data->dma.channel); in flash_stm32_qspi_init()
1387 hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, in flash_stm32_qspi_init()
1388 dev_data->dma.channel); in flash_stm32_qspi_init()
1390 hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg, in flash_stm32_qspi_init()
1391 dev_data->dma.channel-1); in flash_stm32_qspi_init()
1396 __HAL_LINKDMA(&dev_data->hqspi, hdma, hdma); in flash_stm32_qspi_init()
1403 (clock_control_subsys_t) &dev_cfg->pclken) != 0) { in flash_stm32_qspi_init()
1405 return -EIO; in flash_stm32_qspi_init()
1409 (clock_control_subsys_t) &dev_cfg->pclken, in flash_stm32_qspi_init()
1412 return -EIO; in flash_stm32_qspi_init()
1418 if (clk <= dev_cfg->max_frequency) { in flash_stm32_qspi_init()
1424 dev_data->hqspi.Init.ClockPrescaler = prescaler; in flash_stm32_qspi_init()
1426 dev_data->hqspi.Init.FlashSize = find_lsb_set(dev_cfg->flash_size) - 2; in flash_stm32_qspi_init()
1429 * When the DTS has <dual-flash>, it means Dual Flash Mode in flash_stm32_qspi_init()
1430 * Even in DUAL flash config, the SDFP is read from one single quad-NOR in flash_stm32_qspi_init()
1434 dev_data->hqspi.Init.SampleShifting = QSPI_SAMPLE_SHIFTING_HALFCYCLE; in flash_stm32_qspi_init()
1435 dev_data->hqspi.Init.ChipSelectHighTime = QSPI_CS_HIGH_TIME_3_CYCLE; in flash_stm32_qspi_init()
1436 dev_data->hqspi.Init.DualFlash = QSPI_DUALFLASH_DISABLE; in flash_stm32_qspi_init()
1437 /* Set Dual Flash Mode only on MemoryMapped */ in flash_stm32_qspi_init()
1438 dev_data->hqspi.Init.FlashID = QSPI_FLASH_ID_1; in flash_stm32_qspi_init()
1441 HAL_QSPI_Init(&dev_data->hqspi); in flash_stm32_qspi_init()
1447 * does not support Dual-Flash Mode in flash_stm32_qspi_init()
1451 HAL_QSPI_SetFlashID(&dev_data->hqspi, in flash_stm32_qspi_init()
1452 (qspi_flash_id - 1) << QUADSPI_CR_FSEL_Pos); in flash_stm32_qspi_init()
1455 k_sem_init(&dev_data->sem, 1, 1); in flash_stm32_qspi_init()
1456 k_sem_init(&dev_data->sync, 0, 1); in flash_stm32_qspi_init()
1459 dev_cfg->irq_config(dev); in flash_stm32_qspi_init()
1485 return -EINVAL; in flash_stm32_qspi_init()
1488 LOG_INF("%s: SFDP v %u.%u AP %x with %u PH", dev->name, in flash_stm32_qspi_init()
1489 hp->rev_major, hp->rev_minor, hp->access, 1 + hp->nph); in flash_stm32_qspi_init()
1491 const struct jesd216_param_header *php = hp->phdr; in flash_stm32_qspi_init()
1493 MIN(decl_nph, 1 + hp->nph); in flash_stm32_qspi_init()
1499 (php - hp->phdr), id, php->rev_major, php->rev_minor, in flash_stm32_qspi_init()
1500 php->len_dw, jesd216_param_addr(php)); in flash_stm32_qspi_init()
1511 MIN(sizeof(uint32_t) * php->len_dw, sizeof(u2.dw))); in flash_stm32_qspi_init()
1528 return -ENODEV; in flash_stm32_qspi_init()
1535 return -ENODEV; in flash_stm32_qspi_init()
1537 LOG_DBG("Write Un-protected"); in flash_stm32_qspi_init()
1542 * When the DTS has dual_flash, it means Dual Flash Mode for Memory MAPPED in flash_stm32_qspi_init()
1543 * Force Dual Flash mode now, after the SFDP sequence which is reading in flash_stm32_qspi_init()
1544 * one quad-NOR only in flash_stm32_qspi_init()
1546 MODIFY_REG(dev_data->hqspi.Instance->CR, (QUADSPI_CR_DFM), QSPI_DUALFLASH_ENABLE); in flash_stm32_qspi_init()
1547 LOG_DBG("Dual Flash Mode"); in flash_stm32_qspi_init()
1552 LOG_ERR("Failed to enable memory-mapped mode: %d", ret); in flash_stm32_qspi_init()
1555 LOG_INF("Memory-mapped NOR quad-flash at 0x%lx (0x%x bytes)", in flash_stm32_qspi_init()
1557 dev_cfg->flash_size); in flash_stm32_qspi_init()
1559 LOG_INF("NOR quad-flash at 0x%lx (0x%x bytes)", in flash_stm32_qspi_init()
1561 dev_cfg->flash_size); in flash_stm32_qspi_init()