7  * SPDX-License-Identifier: Apache-2.0
37 	 * between them based on the presence of the PECR register. */
66 	if (FLASH_STM32_REGS(dev)->FLASH_STM32_SR & FLASH_STM32_SR_ERRORS) {  in flash_stm32_check_status()
68 			(unsigned long)FLASH_STM32_REGS(dev)->FLASH_STM32_SR &  in flash_stm32_check_status()
71 		FLASH_STM32_REGS(dev)->FLASH_STM32_SR = FLASH_STM32_REGS(dev)->FLASH_STM32_SR &  in flash_stm32_check_status()
73 		return -EIO;  in flash_stm32_check_status()
88 		return -EIO;  in flash_stm32_wait_flash_idle()
98 	while ((FLASH_STM32_REGS(dev)->FLASH_STM32_SR & busy_flags)) {  in flash_stm32_wait_flash_idle()
101 			return -EIO;  in flash_stm32_wait_flash_idle()
126 	if (regs->ACR & FLASH_ACR_DCEN) {  in flash_stm32_flush_caches()
127 		regs->ACR &= ~FLASH_ACR_DCEN;  in flash_stm32_flush_caches()
128 		regs->ACR |= FLASH_ACR_DCRST;  in flash_stm32_flush_caches()
129 		regs->ACR &= ~FLASH_ACR_DCRST;  in flash_stm32_flush_caches()
130 		regs->ACR |= FLASH_ACR_DCEN;  in flash_stm32_flush_caches()
143 		LOG_ERR("Read range invalid. Offset: %ld, len: %zu",  in flash_stm32_read()
145 		return -EINVAL;  in flash_stm32_read()
165 		LOG_ERR("Erase range invalid. Offset: %ld, len: %zu",  in flash_stm32_erase()
167 		return -EINVAL;  in flash_stm32_erase()
202 		LOG_ERR("Write range invalid. Offset: %ld, len: %zu",  in flash_stm32_write()
204 		return -EINVAL;  in flash_stm32_write()
247 		regs->NSCR |= FLASH_STM32_NSLOCK;  in flash_stm32_write_protection()
249 		if (regs->NSCR & FLASH_STM32_NSLOCK) {  in flash_stm32_write_protection()
250 			regs->NSKEYR = FLASH_KEY1;  in flash_stm32_write_protection()
251 			regs->NSKEYR = FLASH_KEY2;  in flash_stm32_write_protection()
256 		regs->CR |= FLASH_CR_LOCK;  in flash_stm32_write_protection()
258 		if (regs->CR & FLASH_CR_LOCK) {  in flash_stm32_write_protection()
259 			regs->KEYR = FLASH_KEY1;  in flash_stm32_write_protection()
260 			regs->KEYR = FLASH_KEY2;  in flash_stm32_write_protection()
265 		regs->PECR |= FLASH_PECR_PRGLOCK;  in flash_stm32_write_protection()
266 		regs->PECR |= FLASH_PECR_PELOCK;  in flash_stm32_write_protection()
268 		if (regs->PECR & FLASH_PECR_PRGLOCK) {  in flash_stm32_write_protection()
270 			regs->PEKEYR = FLASH_PEKEY1;  in flash_stm32_write_protection()
271 			regs->PEKEYR = FLASH_PEKEY2;  in flash_stm32_write_protection()
272 			regs->PRGKEYR = FLASH_PRGKEY1;  in flash_stm32_write_protection()
273 			regs->PRGKEYR = FLASH_PRGKEY2;  in flash_stm32_write_protection()
275 		if (FLASH->PECR & FLASH_PECR_PRGLOCK) {  in flash_stm32_write_protection()
277 			rc = -EIO;  in flash_stm32_write_protection()
297 		regs->OPTCR |= FLASH_OPTCR_OPTLOCK;  in flash_stm32_option_bytes_lock()
298 	} else if (regs->OPTCR & FLASH_OPTCR_OPTLOCK) {  in flash_stm32_option_bytes_lock()
299 		regs->OPTKEYR = FLASH_OPT_KEY1;  in flash_stm32_option_bytes_lock()
300 		regs->OPTKEYR = FLASH_OPT_KEY2;  in flash_stm32_option_bytes_lock()
314 		regs->CR &= ~FLASH_CR_OPTWRE;  in flash_stm32_option_bytes_lock()
315 	} else if (!(regs->CR & FLASH_CR_OPTWRE)) {  in flash_stm32_option_bytes_lock()
316 		regs->OPTKEYR = FLASH_OPTKEY1;  in flash_stm32_option_bytes_lock()
317 		regs->OPTKEYR = FLASH_OPTKEY2;  in flash_stm32_option_bytes_lock()
321 		regs->CR |= FLASH_CR_OPTLOCK;  in flash_stm32_option_bytes_lock()
322 	} else if (regs->CR & FLASH_CR_OPTLOCK) {  in flash_stm32_option_bytes_lock()
323 		regs->OPTKEYR = FLASH_OPTKEY1;  in flash_stm32_option_bytes_lock()
324 		regs->OPTKEYR = FLASH_OPTKEY2;  in flash_stm32_option_bytes_lock()
328 		regs->PECR |= FLASH_PECR_OPTLOCK;  in flash_stm32_option_bytes_lock()
329 	} else if (regs->PECR & FLASH_PECR_OPTLOCK) {  in flash_stm32_option_bytes_lock()
330 		regs->OPTKEYR = FLASH_OPTKEY1;  in flash_stm32_option_bytes_lock()
331 		regs->OPTKEYR = FLASH_OPTKEY2;  in flash_stm32_option_bytes_lock()
335 		regs->NSCR |= FLASH_NSCR_OPTLOCK;  in flash_stm32_option_bytes_lock()
336 	} else if (regs->NSCR & FLASH_NSCR_OPTLOCK) {  in flash_stm32_option_bytes_lock()
337 		regs->OPTKEYR = FLASH_OPTKEY1;  in flash_stm32_option_bytes_lock()
338 		regs->OPTKEYR = FLASH_OPTKEY2;  in flash_stm32_option_bytes_lock()
342 		regs->NSCR1 |= FLASH_NSCR1_OPTLOCK;  in flash_stm32_option_bytes_lock()
343 	} else if (regs->NSCR1 & FLASH_NSCR1_OPTLOCK) {  in flash_stm32_option_bytes_lock()
344 		regs->OPTKEYR = FLASH_OPTKEY1;  in flash_stm32_option_bytes_lock()
345 		regs->OPTKEYR = FLASH_OPTKEY2;  in flash_stm32_option_bytes_lock()
373 	 * Access to control register can be disabled by writing wrong key to  in flash_stm32_control_register_disable()
374 	 * the key register. Option register will remain disabled until reset.  in flash_stm32_control_register_disable()
379 	regs->CR |= FLASH_CR_LOCK;  in flash_stm32_control_register_disable()
382 	regs->KEYR = 0xffffffff;  in flash_stm32_control_register_disable()
385 	SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;  in flash_stm32_control_register_disable()
392 	return -ENOTSUP;  in flash_stm32_control_register_disable()
402 	 * Access to option register can be disabled by writing wrong key to  in flash_stm32_option_bytes_disable()
403 	 * the key register. Option register will remain disabled until reset.  in flash_stm32_option_bytes_disable()
408 	regs->OPTCR |= FLASH_OPTCR_OPTLOCK;  in flash_stm32_option_bytes_disable()
411 	regs->OPTKEYR = 0xffffffff;  in flash_stm32_option_bytes_disable()
414 	SCB->SHCSR &= ~SCB_SHCSR_BUSFAULTPENDED_Msk;  in flash_stm32_option_bytes_disable()
421 	return -ENOTSUP;  in flash_stm32_option_bytes_disable()
437 	 * on the presence of 'clocks' property.
471 	 * On STM32 F0, F1, F3 & L1 series, flash interface clock source is  in stm32_flash_init()
486 		return -ENODEV;  in stm32_flash_init()
490 	if (clock_control_on(clk, (clock_control_subsys_t)&p->pclken) != 0) {  in stm32_flash_init()
492 		return -EIO;  in stm32_flash_init()