4  * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
23 	((struct fiu_reg *)((const struct npcx_qspi_fiu_config *)(dev)->config)->base)
41 	/* Current Software controlled Chip-Select number */
43 	/* Current QSPI bus operation */
44 	uint32_t operation;  member
47 /* NPCX SPI User Mode Access (UMA) functions */
54 		inst->UMA_ECTS |= BIT(sw_cs);  in qspi_npcx_uma_cs_level()
56 		inst->UMA_ECTS &= ~BIT(sw_cs);  in qspi_npcx_uma_cs_level()
65 	inst->UMA_CODE = data;  in qspi_npcx_uma_write_byte()
66 	inst->UMA_CTS = UMA_CODE_CMD_WR_ONLY;  in qspi_npcx_uma_write_byte()
68 	while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) {  in qspi_npcx_uma_write_byte()
78 	inst->UMA_CTS = UMA_CODE_RD_BYTE(1);  in qspi_npcx_uma_read_byte()
79 	while (IS_BIT_SET(inst->UMA_CTS, NPCX_UMA_CTS_EXEC_DONE)) {  in qspi_npcx_uma_read_byte()
83 	*data = inst->UMA_DB0;  in qspi_npcx_uma_read_byte()
86 /* NPCX SPI Direct Read Access (DRA)/User Mode Access (UMA) configuration functions */
92 	if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {  in qspi_npcx_config_uma_mode()
93 		inst->UMA_ECTS |= BIT(NPCX_UMA_ECTS_SEC_CS);  in qspi_npcx_config_uma_mode()
95 		inst->UMA_ECTS &= ~BIT(NPCX_UMA_ECTS_SEC_CS);  in qspi_npcx_config_uma_mode()
106 	if (qspi_cfg->enter_4ba != 0) {  in qspi_npcx_config_dra_4byte_mode()
107 		if ((qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0) {  in qspi_npcx_config_dra_4byte_mode()
108 			inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11);  in qspi_npcx_config_dra_4byte_mode()
110 			inst->SPI1_DEV |= BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS10);  in qspi_npcx_config_dra_4byte_mode()
113 		inst->SPI1_DEV &= ~(BIT(NPCX_SPI1_DEV_FOUR_BADDR_CS11) |  in qspi_npcx_config_dra_4byte_mode()
117 	if (qspi_cfg->enter_4ba != 0) {  in qspi_npcx_config_dra_4byte_mode()
118 		SET_FIELD(inst->SPI_DEV, NPCX_SPI_DEV_NADDRB, NPCX_DEV_NUM_ADDR_4BYTE);  in qspi_npcx_config_dra_4byte_mode()
129 	/* Select SPI device number for DRA mode in npcx4 series */  in qspi_npcx_config_dra_mode()
131 		int spi_dev_num = (qspi_cfg->flags & NPCX_QSPI_SEC_FLASH_SL) != 0 ? 1 : 0;  in qspi_npcx_config_dra_mode()
133 		SET_FIELD(inst->BURST_CFG, NPCX_BURST_CFG_SPI_DEV_SEL, spi_dev_num);  in qspi_npcx_config_dra_mode()
136 	/* Enable quad mode of Direct Read Mode if needed */  in qspi_npcx_config_dra_mode()
137 	if (qspi_cfg->qer_type != JESD216_DW15_QER_NONE) {  in qspi_npcx_config_dra_mode()
138 		inst->RESP_CFG |= BIT(NPCX_RESP_CFG_QUAD_EN);  in qspi_npcx_config_dra_mode()
140 		inst->RESP_CFG &= ~BIT(NPCX_RESP_CFG_QUAD_EN);  in qspi_npcx_config_dra_mode()
143 	/* Selects the SPI read access type of Direct Read Access mode */  in qspi_npcx_config_dra_mode()
144 	SET_FIELD(inst->SPI_FL_CFG, NPCX_SPI_FL_CFG_RD_MODE, qspi_cfg->rd_mode);  in qspi_npcx_config_dra_mode()
146 	/* Enable/Disable 4 byte address mode for Direct Read Access (DRA) */  in qspi_npcx_config_dra_mode()
150 static inline void qspi_npcx_fiu_set_operation(const struct device *dev, uint32_t operation)  in qspi_npcx_fiu_set_operation()  argument
152 	if ((operation & NPCX_EX_OP_INT_FLASH_WP) != 0) {  in qspi_npcx_fiu_set_operation()
157 /* NPCX specific QSPI-FIU controller functions */
161 	struct npcx_qspi_fiu_data *const data = dev->data;  in qspi_npcx_fiu_uma_transceive()
164 	if ((data->operation & NPCX_EX_OP_LOCK_UMA) != 0) {  in qspi_npcx_fiu_uma_transceive()
165 		return -EPERM;  in qspi_npcx_fiu_uma_transceive()
169 	qspi_npcx_uma_cs_level(dev, data->sw_cs, false);  in qspi_npcx_fiu_uma_transceive()
171 	/* Transmit op-code first */  in qspi_npcx_fiu_uma_transceive()
172 	qspi_npcx_uma_write_byte(dev, cfg->opcode);  in qspi_npcx_fiu_uma_transceive()
175 		/* 3-byte or 4-byte address? */  in qspi_npcx_fiu_uma_transceive()
176 		const int addr_start = (data->cur_cfg->enter_4ba != 0) ? 0 : 1;  in qspi_npcx_fiu_uma_transceive()
179 			LOG_DBG("addr %d, %02x", i, cfg->addr.u8[i]);  in qspi_npcx_fiu_uma_transceive()
180 			qspi_npcx_uma_write_byte(dev, cfg->addr.u8[i]);  in qspi_npcx_fiu_uma_transceive()
185 		if (cfg->tx_buf == NULL) {  in qspi_npcx_fiu_uma_transceive()
186 			return -EINVAL;  in qspi_npcx_fiu_uma_transceive()
188 		for (size_t i = 0; i < cfg->tx_count; i++) {  in qspi_npcx_fiu_uma_transceive()
189 			qspi_npcx_uma_write_byte(dev, cfg->tx_buf[i]);  in qspi_npcx_fiu_uma_transceive()
194 		if (cfg->rx_buf == NULL) {  in qspi_npcx_fiu_uma_transceive()
195 			return -EINVAL;  in qspi_npcx_fiu_uma_transceive()
197 		for (size_t i = 0; i < cfg->rx_count; i++) {  in qspi_npcx_fiu_uma_transceive()
198 			qspi_npcx_uma_read_byte(dev, cfg->rx_buf + i);  in qspi_npcx_fiu_uma_transceive()
202 	/* De-assert chip select */  in qspi_npcx_fiu_uma_transceive()
203 	qspi_npcx_uma_cs_level(dev, data->sw_cs, true);  in qspi_npcx_fiu_uma_transceive()
210 					const uint32_t operation)  in qspi_npcx_fiu_mutex_lock_configure()  argument
212 	struct npcx_qspi_fiu_data *const data = dev->data;  in qspi_npcx_fiu_mutex_lock_configure()
214 	k_sem_take(&data->lock_sem, K_FOREVER);  in qspi_npcx_fiu_mutex_lock_configure()
217 	if (data->cur_cfg != cfg) {  in qspi_npcx_fiu_mutex_lock_configure()
218 		data->cur_cfg = cfg;  in qspi_npcx_fiu_mutex_lock_configure()
220 		/* Apply pin-muxing and tri-state */  in qspi_npcx_fiu_mutex_lock_configure()
221 		pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);  in qspi_npcx_fiu_mutex_lock_configure()
223 		/* Configure User Mode Access (UMA) settings */  in qspi_npcx_fiu_mutex_lock_configure()
229 		/* Save SW CS bit used in UMA mode */  in qspi_npcx_fiu_mutex_lock_configure()
230 		data->sw_cs = find_lsb_set(cfg->flags & NPCX_QSPI_SW_CS_MASK) - 1;  in qspi_npcx_fiu_mutex_lock_configure()
233 	/* Set QSPI bus operation */  in qspi_npcx_fiu_mutex_lock_configure()
234 	if (data->operation != operation) {  in qspi_npcx_fiu_mutex_lock_configure()
235 		qspi_npcx_fiu_set_operation(dev, operation);  in qspi_npcx_fiu_mutex_lock_configure()
236 		data->operation = operation;  in qspi_npcx_fiu_mutex_lock_configure()
242 	struct npcx_qspi_fiu_data *const data = dev->data;  in qspi_npcx_fiu_mutex_unlock()
244 	k_sem_give(&data->lock_sem);  in qspi_npcx_fiu_mutex_unlock()
249 	const struct npcx_qspi_fiu_config *const config = dev->config;  in qspi_npcx_fiu_init()
250 	struct npcx_qspi_fiu_data *const data = dev->data;  in qspi_npcx_fiu_init()
255 		LOG_ERR("%s device not ready", clk_dev->name);  in qspi_npcx_fiu_init()
256 		return -ENODEV;  in qspi_npcx_fiu_init()
261 			       (clock_control_subsys_t)&config->clk_cfg);  in qspi_npcx_fiu_init()
268 	k_sem_init(&data->lock_sem, 1, 1);  in qspi_npcx_fiu_init()
271 	if (config->en_direct_access_2dev) {  in qspi_npcx_fiu_init()
275 		inst->FIU_EXT_CFG |= BIT(NPCX_FIU_EXT_CFG_SPI1_2DEV);  in qspi_npcx_fiu_init()