Lines Matching +full:spi +full:- +full:addr
4 * SPDX-License-Identifier: Apache-2.0
13 #include <zephyr/dt-bindings/flash_controller/npcx_fiu_qspi.h>
37 /* Maximum chip erase time-out in ms */
39 /* SPI Nor device configuration on QSPI bus */
48 /* Specific control operation for Quad-SPI Nor Flash */
63 static inline bool is_within_region(off_t addr, size_t size, off_t region_start, in is_within_region() argument
66 return (addr >= region_start && in is_within_region()
67 (addr < (region_start + region_size)) && in is_within_region()
68 ((addr + size) <= (region_start + region_size))); in is_within_region()
74 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_uma_transceive()
75 struct flash_npcx_nor_data *data = dev->data; in flash_npcx_uma_transceive()
78 /* Lock SPI bus and configure it if needed */ in flash_npcx_uma_transceive()
79 qspi_npcx_fiu_mutex_lock_configure(config->qspi_bus, &config->qspi_cfg, in flash_npcx_uma_transceive()
80 data->operation); in flash_npcx_uma_transceive()
83 ret = qspi_npcx_fiu_uma_transceive(config->qspi_bus, cfg, flags); in flash_npcx_uma_transceive()
85 /* Unlock SPI bus */ in flash_npcx_uma_transceive()
86 qspi_npcx_fiu_mutex_unlock(config->qspi_bus); in flash_npcx_uma_transceive()
91 /* NPCX UMA functions for SPI NOR flash */
100 uint32_t addr) in flash_npcx_uma_cmd_by_addr() argument
104 cfg.addr.u32 = sys_cpu_to_be32(addr); in flash_npcx_uma_cmd_by_addr()
129 uint8_t *src, const size_t size, uint32_t addr) in flash_npcx_uma_write_by_addr() argument
135 cfg.addr.u32 = sys_cpu_to_be32(addr); in flash_npcx_uma_write_by_addr()
140 /* Local SPI NOR flash functions */
145 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_nor_wait_until_ready()
156 } while ((k_uptime_get() - st) < config->max_timeout); in flash_npcx_nor_wait_until_ready()
158 return -EBUSY; in flash_npcx_nor_wait_until_ready()
193 return -EINVAL; in flash_npcx_nor_read_jedec_id()
199 static int flash_npcx_nor_read_sfdp(const struct device *dev, off_t addr, in flash_npcx_nor_read_sfdp() argument
210 return -EINVAL; in flash_npcx_nor_read_sfdp()
213 /* CMD_READ_SFDP needs a 24-bit address followed by a dummy byte */ in flash_npcx_nor_read_sfdp()
214 sfdp_addr[0] = (addr >> 16) & 0xff; in flash_npcx_nor_read_sfdp()
215 sfdp_addr[1] = (addr >> 8) & 0xff; in flash_npcx_nor_read_sfdp()
216 sfdp_addr[2] = addr & 0xff; in flash_npcx_nor_read_sfdp()
227 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_nor_pages_layout()
229 *layout = &config->layout; in flash_npcx_nor_pages_layout()
234 static int flash_npcx_nor_read(const struct device *dev, off_t addr, in flash_npcx_nor_read() argument
237 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_nor_read()
238 struct flash_npcx_nor_data *dev_data = dev->data; in flash_npcx_nor_read()
241 if (!is_within_region(addr, size, 0, config->flash_size)) { in flash_npcx_nor_read()
242 return -EINVAL; in flash_npcx_nor_read()
245 /* Lock/Unlock SPI bus also for DRA mode */ in flash_npcx_nor_read()
246 qspi_npcx_fiu_mutex_lock_configure(config->qspi_bus, &config->qspi_cfg, in flash_npcx_nor_read()
247 dev_data->operation); in flash_npcx_nor_read()
249 /* Trigger Direct Read Access (DRA) via reading memory mapped-address */ in flash_npcx_nor_read()
250 memcpy(data, (void *)(config->mapped_addr + addr), size); in flash_npcx_nor_read()
252 qspi_npcx_fiu_mutex_unlock(config->qspi_bus); in flash_npcx_nor_read()
257 static int flash_npcx_nor_erase(const struct device *dev, off_t addr, size_t size) in flash_npcx_nor_erase() argument
259 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_nor_erase()
263 if (!is_within_region(addr, size, 0, config->flash_size)) { in flash_npcx_nor_erase()
264 LOG_ERR("Addr %ld, size %d are out of range", addr, size); in flash_npcx_nor_erase()
265 return -EINVAL; in flash_npcx_nor_erase()
268 /* address must be sector-aligned */ in flash_npcx_nor_erase()
269 if (!SPI_NOR_IS_SECTOR_ALIGNED(addr)) { in flash_npcx_nor_erase()
270 LOG_ERR("Addr %ld is not sector-aligned", addr); in flash_npcx_nor_erase()
271 return -EINVAL; in flash_npcx_nor_erase()
277 return -EINVAL; in flash_npcx_nor_erase()
281 if (size == config->flash_size) { in flash_npcx_nor_erase()
290 /* Send page/block erase command with addr */ in flash_npcx_nor_erase()
291 if ((size >= BLOCK_64K_SIZE) && SPI_NOR_IS_64K_ALIGNED(addr)) { in flash_npcx_nor_erase()
292 flash_npcx_uma_cmd_by_addr(dev, SPI_NOR_CMD_BE, addr); in flash_npcx_nor_erase()
293 addr += BLOCK_64K_SIZE; in flash_npcx_nor_erase()
294 size -= BLOCK_64K_SIZE; in flash_npcx_nor_erase()
296 flash_npcx_uma_cmd_by_addr(dev, SPI_NOR_CMD_SE, addr); in flash_npcx_nor_erase()
297 addr += BLOCK_4K_SIZE; in flash_npcx_nor_erase()
298 size -= BLOCK_4K_SIZE; in flash_npcx_nor_erase()
309 static int flash_npcx_nor_write(const struct device *dev, off_t addr, in flash_npcx_nor_write() argument
312 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_nor_write()
318 if (!is_within_region(addr, size, 0, config->flash_size)) { in flash_npcx_nor_write()
319 return -EINVAL; in flash_npcx_nor_write()
333 if (((addr + sz_write - 1U) / SPI_NOR_PAGE_SIZE) != (addr / SPI_NOR_PAGE_SIZE)) { in flash_npcx_nor_write()
334 sz_write -= (addr + sz_write) & (SPI_NOR_PAGE_SIZE - 1); in flash_npcx_nor_write()
341 sz_write, addr); in flash_npcx_nor_write()
352 size -= sz_write; in flash_npcx_nor_write()
354 addr += sz_write; in flash_npcx_nor_write()
383 return -EINVAL; in flash_npcx_nor_ex_exec_uma()
387 cfg.opcode = op_in->opcode; in flash_npcx_nor_ex_exec_uma()
388 if (op_in->tx_count != 0) { in flash_npcx_nor_ex_exec_uma()
389 cfg.tx_buf = op_in->tx_buf; in flash_npcx_nor_ex_exec_uma()
390 cfg.tx_count = op_in->tx_count; in flash_npcx_nor_ex_exec_uma()
394 if (op_in->addr_count != 0) { in flash_npcx_nor_ex_exec_uma()
395 cfg.addr.u32 = sys_cpu_to_be32(op_in->addr); in flash_npcx_nor_ex_exec_uma()
399 if (op_out != NULL && op_in->rx_count != 0) { in flash_npcx_nor_ex_exec_uma()
400 cfg.rx_buf = op_out->rx_buf; in flash_npcx_nor_ex_exec_uma()
401 cfg.rx_count = op_in->rx_count; in flash_npcx_nor_ex_exec_uma()
411 struct flash_npcx_nor_data *data = dev->data; in flash_npcx_nor_ex_set_spi_spec()
414 if ((data->operation & NPCX_EX_OP_INT_FLASH_WP) != 0) { in flash_npcx_nor_ex_set_spi_spec()
415 if ((op_in->mask & NPCX_EX_OP_INT_FLASH_WP) != 0 && !op_in->enable) { in flash_npcx_nor_ex_set_spi_spec()
416 return -EINVAL; in flash_npcx_nor_ex_set_spi_spec()
420 if (op_in->enable) { in flash_npcx_nor_ex_set_spi_spec()
421 data->operation |= op_in->mask; in flash_npcx_nor_ex_set_spi_spec()
423 data->operation &= ~op_in->mask; in flash_npcx_nor_ex_set_spi_spec()
432 struct flash_npcx_nor_data *data = dev->data; in flash_npcx_nor_ex_get_spi_spec()
434 op_out->oper = data->operation; in flash_npcx_nor_ex_get_spi_spec()
504 ret = -ENOTSUP; in flash_npcx_nor_ex_op()
531 const struct flash_npcx_nor_config *config = dev->config; in flash_npcx_nor_init()
538 /* Enable quad access of spi NOR flash */ in flash_npcx_nor_init()
539 if (config->qspi_cfg.qer_type != JESD216_DW15_QER_NONE) { in flash_npcx_nor_init()
547 switch (config->qspi_cfg.qer_type) { in flash_npcx_nor_init()
561 return -ENOTSUP; in flash_npcx_nor_init()
564 sts_reg[qe_idx - 1] |= BIT(qe_bit); in flash_npcx_nor_init()
572 /* Enable 4-byte address of spi NOR flash */ in flash_npcx_nor_init()
573 if (config->qspi_cfg.enter_4ba != 0) { in flash_npcx_nor_init()
574 bool wr_en = (config->qspi_cfg.enter_4ba & 0x02) != 0; in flash_npcx_nor_init()
579 LOG_ERR("Enable 4byte addr: WREN failed %d!", ret); in flash_npcx_nor_init()
585 LOG_ERR("Enable 4byte addr: 4BA failed %d!", ret); in flash_npcx_nor_init()