Lines Matching +full:sector +full:- +full:0 +full:a +full:- +full:pages
5 * SPDX-License-Identifier: Apache-2.0
9 #define SOC_NV_FLASH_NODE DT_PARENT(DT_INST(0, fixed_partitions))
37 .erase_value = 0xFF,
40 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_cmd = {0};
42 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_en_cmd = {0};
44 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_dis_cmd = {0};
46 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_erase_cmd = {0};
48 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_chip_erase_cmd = {0};
50 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_program_cmd = {0};
52 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_qe_cmd = {0};
54 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_wip_cmd = {0};
56 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_qe_cmd = {0};
58 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_sts_reg_oe_cmd = {0};
60 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_sts_reg_oe_cmd = {0};
62 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_read_latency_cmd = {0};
64 cy_stc_smif_mem_cmd_t sfdp_slave_slot_0_write_latency_cmd = {0};
67 /* The 8-bit command. 1 x I/O read command. */
68 .command = 0x5AU,
73 /* The 8-bit mode byte. This value is 0xFFFFFFFF when there is no mode present. */
74 .mode = 0xFFFFFFFFU,
77 /* The number of dummy cycles. A zero value suggests no dummy cycles. */
86 .cmdSeq1 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
87 .cmdSeq2 = {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
92 * https://iot-webserver.aus.cypress.com/projects/iot_release/
93 * ASSETS/repo/mtb-pdl-cat1/develop/Latest/deploy/docs/
108 .numOfAddrBytes = 0x03U,
110 .memSize = 0x0000100U,
119 /* Specifies the sector size of each erase. */
120 .eraseSize = 0x0001000U,
126 .programSize = 0x0000100U,
127 /* Specifies the command to read the QE-containing status register. */
129 /* Specifies the command to read the WIP-containing status register. */
133 /* Specifies the command to write into the QE-containing status register. */
136 .stsRegBusyMask = 0x00U,
138 .stsRegQuadEnableMask = 0x00U,
139 /* The max time for the erase type-1 cycle-time in ms. */
141 /* The max time for the chip-erase cycle-time in ms. */
143 /* The max time for the page-program cycle-time in us. */
147 .hybridRegionCount = 0U,
155 .latencyCyclesRegAddr = 0x00U,
157 .latencyCyclesMask = 0x00U,
160 /* Specifies the command to read the OE-containing status register. */
162 /* Specifies the command to write the OE-containing status register. */
165 .stsRegOctalEnableMask = 0x00U,
167 .octalEnableRegAddr = 0x00U,
178 /* The data-line selection options for a slave device. */
181 * Valid when the memory-mapped mode is enabled.
183 .baseAddress = 0x60000000U,
188 .memMappedSize = 0x100000U,
192 .dualQuadSlots = 0,
196 * After this period the memory device is deselected. A later transfer, even from a
205 struct ifx_cat1_flash_data *data = dev->data; in flash_ifx_sem_take()
207 k_sem_take(&data->sem, K_FOREVER); in flash_ifx_sem_take()
212 struct ifx_cat1_flash_data *data = dev->data; in flash_ifx_sem_give()
214 k_sem_give(&data->sem); in flash_ifx_sem_give()
220 int ret = 0; in ifx_cat1_flash_read()
223 return 0; in ifx_cat1_flash_read()
230 LOG_ERR("Error reading @ %lu (Err:0x%x)", offset, rslt); in ifx_cat1_flash_read()
231 ret = -EIO; in ifx_cat1_flash_read()
242 int ret = 0; in ifx_cat1_flash_write()
244 if (data_len == 0) { in ifx_cat1_flash_write()
245 return 0; in ifx_cat1_flash_write()
248 if (offset < 0) { in ifx_cat1_flash_write()
249 return -EINVAL; in ifx_cat1_flash_write()
256 LOG_ERR("Error in writing @ %lu (Err:0x%x)", offset, rslt); in ifx_cat1_flash_write()
257 ret = -EIO; in ifx_cat1_flash_write()
267 int ret = 0; in ifx_cat1_flash_erase()
269 if (offset < 0) { in ifx_cat1_flash_erase()
270 return -EINVAL; in ifx_cat1_flash_erase()
277 LOG_ERR("Error in erasing : 0x%x", rslt); in ifx_cat1_flash_erase()
278 ret = -EIO; in ifx_cat1_flash_erase()
300 * number of pages in the memory. in ifx_cat1_flash_page_layout()
315 struct ifx_cat1_flash_data *data = dev->data; in ifx_cat1_flash_init()
321 LOG_ERR("Serial Flash initialization failed [rslt: 0x%x]", rslt); in ifx_cat1_flash_init()
324 k_sem_init(&data->sem, 1, 1); in ifx_cat1_flash_init()
326 return 0; in ifx_cat1_flash_init()
345 DEVICE_DT_INST_DEFINE(0, ifx_cat1_flash_init, NULL, &flash_data, &flash_config, POST_KERNEL,