Lines Matching +full:0 +full:xb9

8 #define FLASH_ANDES_CMD_WRSR	0x01    /* Write status register */
9 #define FLASH_ANDES_CMD_RDSR	0x05    /* Read status register */
10 #define FLASH_ANDES_CMD_READ	0x03    /* Read data */
11 #define FLASH_ANDES_CMD_4READ	0xEB    /* Quad mode Read data*/
12 #define FLASH_ANDES_CMD_WREN	0x06    /* Write enable */
13 #define FLASH_ANDES_CMD_WRDI	0x04    /* Write disable */
14 #define FLASH_ANDES_CMD_PP	0x02    /* Page program */
15 #define FLASH_ANDES_CMD_4PP	0x38    /* Quad mode page program*/
16 #define FLASH_ANDES_CMD_SE	0x20    /* Sector erase */
17 #define FLASH_ANDES_CMD_BE_32K	0x52    /* Block erase 32KB */
18 #define FLASH_ANDES_CMD_BE	0xD8    /* Block erase */
19 #define FLASH_ANDES_CMD_CE	0xC7    /* Chip erase */
20 #define FLASH_ANDES_CMD_RDID	0x9F    /* Read JEDEC ID */
21 #define FLASH_ANDES_CMD_ULBPR	0x98    /* Global Block Protection Unlock */
22 #define FLASH_ANDES_CMD_DPD	0xB9    /* Deep Power Down */
23 #define FLASH_ANDES_CMD_RDPD	0xAB    /* Release from Deep Power Down */
26 #define FLASH_ANDES_WIP_BIT	BIT(0)  /* Write in progress */
30 #define QSPI_TFMAT(base)	(base + 0x10)
31 #define QSPI_TCTRL(base)	(base + 0x20)
32 #define QSPI_CMD(base)		(base + 0x24)
33 #define QSPI_ADDR(base)		(base + 0x28)
34 #define QSPI_DATA(base)		(base + 0x2c)
35 #define QSPI_CTRL(base)		(base + 0x30)
36 #define QSPI_STAT(base)		(base + 0x34)
37 #define QSPI_INTEN(base)	(base + 0x38)
38 #define QSPI_INTST(base)	(base + 0x3c)
39 #define QSPI_TIMIN(base)	(base + 0x40)
40 #define QSPI_CONFIG(base)	(base + 0x7c)
51 #define TCTRL_RD_TCNT_OFFSET		(0)
63 #define TRNS_MODE_WRITE_READ		(0 << TCTRL_TRNS_MODE_OFFSET)
74 #define DUMMY_CNT_3			(0x2 << TCTRL_DUMMY_CNT_OFFSET)
87 #define CFG_RX_FIFO_SIZE_MSK		GENMASK(3, 0)
102 #define TIMIN_SCLK_DIV_MSK		GENMASK(7, 0)
116 	(2 << (RX_FIFO_SIZE_SETTING(base) >> 0))