Lines Matching refs:phy_data
201 uint16_t phy_data; in phy_xlnx_gem_marvell_alaska_reset() local
209 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
211 phy_data |= PHY_MRVL_COPPER_CONTROL_RESET_BIT; in phy_xlnx_gem_marvell_alaska_reset()
213 PHY_MRVL_COPPER_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_reset()
216 while (((phy_data & PHY_MRVL_COPPER_CONTROL_RESET_BIT) != 0) && (retries++ < 10)) { in phy_xlnx_gem_marvell_alaska_reset()
217 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
236 uint16_t phy_data; in phy_xlnx_gem_marvell_alaska_cfg() local
247 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
249 phy_data &= ~PHY_MRVL_COPPER_CONTROL_AUTONEG_ENABLE_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
251 PHY_MRVL_COPPER_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
271 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
273 phy_data &= ~(PHY_MRVL_MODE_CONFIG_MASK << PHY_MRVL_MODE_CONFIG_SHIFT); in phy_xlnx_gem_marvell_alaska_cfg()
275 PHY_MRVL_GENERAL_CONTROL_1_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
283 phy_data |= PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
285 PHY_MRVL_GENERAL_CONTROL_1_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
288 while (((phy_data & PHY_MRVL_GENERAL_CONTROL_1_RESET_BIT) != 0) && in phy_xlnx_gem_marvell_alaska_cfg()
290 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, in phy_xlnx_gem_marvell_alaska_cfg()
317 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
319 phy_data &= ~(PHY_MRVL_MDIX_CONFIG_MASK << PHY_MRVL_MDIX_CONFIG_SHIFT); in phy_xlnx_gem_marvell_alaska_cfg()
320 phy_data |= (PHY_MRVL_MDIX_AUTO_CROSSOVER_ENABLE << PHY_MRVL_MDIX_CONFIG_SHIFT); in phy_xlnx_gem_marvell_alaska_cfg()
322 PHY_MRVL_COPPER_CONTROL_1_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
346 phy_data = PHY_MRVL_COPPER_SPEED_CHANGED_INT_BIT | in phy_xlnx_gem_marvell_alaska_cfg()
351 PHY_MRVL_COPPER_INT_ENABLE_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
360 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
395 phy_data = PHY_MRVL_ADV_SELECTOR_802_3; in phy_xlnx_gem_marvell_alaska_cfg()
397 phy_data = 0x0000; in phy_xlnx_gem_marvell_alaska_cfg()
416 phy_data |= PHY_MRVL_ADV_100BASET_FDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
418 phy_data |= PHY_MRVL_ADV_10BASET_FDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
422 phy_data |= PHY_MRVL_ADV_100BASET_FDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
425 phy_data |= PHY_MRVL_ADV_10BASET_FDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
429 phy_data |= PHY_MRVL_ADV_10BASET_FDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
437 phy_data |= PHY_MRVL_ADV_100BASET_HDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
439 phy_data |= PHY_MRVL_ADV_10BASET_HDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
443 phy_data |= PHY_MRVL_ADV_100BASET_HDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
446 phy_data |= PHY_MRVL_ADV_10BASET_HDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
450 phy_data |= PHY_MRVL_ADV_10BASET_HDX_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
457 PHY_MRVL_COPPER_AUTONEG_ADV_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
465 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
467 phy_data |= PHY_MRVL_COPPER_CONTROL_AUTONEG_ENABLE_BIT; in phy_xlnx_gem_marvell_alaska_cfg()
469 PHY_MRVL_COPPER_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_marvell_alaska_cfg()
491 uint16_t phy_data; in phy_xlnx_gem_marvell_alaska_poll_sc() local
504 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_sc()
507 if ((phy_data & PHY_MRVL_COPPER_AUTONEG_COMPLETED_INT_BIT) != 0) { in phy_xlnx_gem_marvell_alaska_poll_sc()
510 if (((phy_data & PHY_MRVL_COPPER_DUPLEX_CHANGED_INT_BIT) != 0) || in phy_xlnx_gem_marvell_alaska_poll_sc()
511 ((phy_data & PHY_MRVL_COPPER_LINK_STATUS_CHANGED_INT_BIT) != 0)) { in phy_xlnx_gem_marvell_alaska_poll_sc()
514 if ((phy_data & PHY_MRVL_COPPER_SPEED_CHANGED_INT_BIT) != 0) { in phy_xlnx_gem_marvell_alaska_poll_sc()
523 PHY_MRVL_COPPER_INT_STATUS_REGISTER, (phy_data & 0x8)); in phy_xlnx_gem_marvell_alaska_poll_sc()
539 uint16_t phy_data; in phy_xlnx_gem_marvell_alaska_poll_lsts() local
546 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_lsts()
549 return ((phy_data >> PHY_MRVL_COPPER_LINK_STATUS_BIT_SHIFT) & 0x0001); in phy_xlnx_gem_marvell_alaska_poll_lsts()
565 uint16_t phy_data; in phy_xlnx_gem_marvell_alaska_poll_lspd() local
572 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_lspd()
574 phy_data >>= PHY_MRVL_LINK_SPEED_SHIFT; in phy_xlnx_gem_marvell_alaska_poll_lspd()
575 phy_data &= PHY_MRVL_LINK_SPEED_MASK; in phy_xlnx_gem_marvell_alaska_poll_lspd()
581 switch (phy_data) { in phy_xlnx_gem_marvell_alaska_poll_lspd()
619 uint16_t phy_data; in phy_xlnx_gem_ti_dp83822_reset() local
622 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_reset()
624 phy_data |= PHY_TI_BASIC_MODE_CONTROL_RESET_BIT; in phy_xlnx_gem_ti_dp83822_reset()
626 PHY_TI_BASIC_MODE_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_ti_dp83822_reset()
628 while (((phy_data & PHY_TI_BASIC_MODE_CONTROL_RESET_BIT) != 0) && (retries++ < 10)) { in phy_xlnx_gem_ti_dp83822_reset()
629 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_reset()
648 uint16_t phy_data = PHY_TI_ADV_SELECTOR_802_3; in phy_xlnx_gem_ti_dp83822_cfg() local
654 phy_data |= PHY_TI_ADV_100BASET_FDX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
657 phy_data |= PHY_TI_ADV_10BASET_FDX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
661 phy_data |= PHY_TI_ADV_10BASET_FDX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
666 phy_data |= PHY_TI_ADV_100BASET_HDX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
669 phy_data |= PHY_TI_ADV_10BASET_HDX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
673 phy_data |= PHY_TI_ADV_10BASET_HDX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
677 PHY_TI_AUTONEG_ADV_REGISTER, phy_data); in phy_xlnx_gem_ti_dp83822_cfg()
680 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
682 phy_data |= PHY_TI_BASIC_MODE_CONTROL_AUTONEG_ENABLE_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
684 PHY_TI_BASIC_MODE_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_ti_dp83822_cfg()
687 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
689 phy_data |= PHY_TI_CR1_ROBUST_AUTO_MDIX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
691 PHY_TI_CONTROL_REGISTER_1, phy_data); in phy_xlnx_gem_ti_dp83822_cfg()
693 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
696 phy_data |= PHY_TI_PHY_CONTROL_AUTO_MDIX_ENABLE_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
698 phy_data |= PHY_TI_PHY_CONTROL_LED_CONFIG_LINK_ONLY_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
700 phy_data &= ~PHY_TI_PHY_CONTROL_FORCE_MDIX_BIT; in phy_xlnx_gem_ti_dp83822_cfg()
702 PHY_TI_PHY_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_ti_dp83822_cfg()
705 phy_data = (PHY_TI_LED_CONTROL_BLINK_RATE_5HZ << in phy_xlnx_gem_ti_dp83822_cfg()
708 PHY_TI_LED_CONTROL_REGISTER, phy_data); in phy_xlnx_gem_ti_dp83822_cfg()
730 uint16_t phy_data; in phy_xlnx_gem_ti_dp83822_poll_sc() local
740 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_sc()
743 if ((phy_data & PHY_TI_AUTONEG_COMPLETED_INT_BIT) != 0) { in phy_xlnx_gem_ti_dp83822_poll_sc()
746 if ((phy_data & PHY_TI_DUPLEX_CHANGED_INT_BIT) != 0) { in phy_xlnx_gem_ti_dp83822_poll_sc()
749 if ((phy_data & PHY_TI_LINK_STATUS_CHANGED_INT_BIT) != 0) { in phy_xlnx_gem_ti_dp83822_poll_sc()
752 if ((phy_data & PHY_TI_SPEED_CHANGED_INT_BIT) != 0) { in phy_xlnx_gem_ti_dp83822_poll_sc()
770 uint16_t phy_data; in phy_xlnx_gem_ti_dp83822_poll_lsts() local
778 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_lsts()
780 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_lsts()
783 return ((phy_data & PHY_TI_BASIC_MODE_STATUS_LINK_STATUS_BIT) != 0); in phy_xlnx_gem_ti_dp83822_poll_lsts()
799 uint16_t phy_data; in phy_xlnx_gem_ti_dp83822_poll_lspd() local
801 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_lspd()
805 if ((phy_data & PHY_TI_PHY_STATUS_LINK_BIT) != 0) { in phy_xlnx_gem_ti_dp83822_poll_lspd()
807 if ((phy_data & PHY_TI_PHY_STATUS_SPEED_BIT) != 0) { in phy_xlnx_gem_ti_dp83822_poll_lspd()
908 uint16_t phy_data; in phy_xlnx_gem_detect() local
933 phy_data = phy_xlnx_gem_mdio_read( in phy_xlnx_gem_detect()
936 phy_id = (((uint32_t)phy_data << 16) & 0xFFFF0000); in phy_xlnx_gem_detect()
937 phy_data = phy_xlnx_gem_mdio_read( in phy_xlnx_gem_detect()
940 phy_id |= ((uint32_t)phy_data & 0x0000FFFF); in phy_xlnx_gem_detect()