Lines Matching +full:auto +full:- +full:detection
6 * - Marvell Alaska 88E1111 (QEMU simulated PHY)
7 * - Marvell Alaska 88E1510/88E1518/88E1512/88E1514 (Zedboard)
8 * - Texas Instruments TLK105
9 * - Texas Instruments DP83822
12 * SPDX-License-Identifier: Apache-2.0
34 * @return 16-bit data word received from the PHY
44 * MDIO read operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_read()
81 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_read()
99 * Read the data returned by the PHY -> lower 16 bits of the PHY main- in phy_xlnx_gem_mdio_read()
113 * @param value 16-bit data word to be written to the target register
123 * MDIO write operation as described in Zynq-7000 TRM, in phy_xlnx_gem_mdio_write()
162 * Wait until gem.net_status[phy_mgmt_idle] == 1 -> current command in phy_xlnx_gem_mdio_write()
180 * Vendor-specific PHY management functions for:
184 …w.marvell.com/content/dam/marvell/en/public-collateral/transceivers/marvell-phys-transceivers-alas…
185 …w.marvell.com/content/dam/marvell/en/public-collateral/transceivers/marvell-phys-transceivers-alas…
199 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_reset()
200 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_marvell_alaska_reset()
209 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
212 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
217 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_reset()
222 dev->name, dev_data->phy_addr); in phy_xlnx_gem_marvell_alaska_reset()
234 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_cfg()
235 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_marvell_alaska_cfg()
242 * bit [12] = auto-negotiation enable bit is to be cleared in phy_xlnx_gem_marvell_alaska_cfg()
247 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
250 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
254 if ((dev_data->phy_id & PHY_MRVL_PHY_ID_MODEL_MASK) == in phy_xlnx_gem_marvell_alaska_cfg()
267 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
271 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
274 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
279 * Reset is performed immediately, bit [15] is self-clearing. in phy_xlnx_gem_marvell_alaska_cfg()
284 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
290 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, in phy_xlnx_gem_marvell_alaska_cfg()
291 dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
296 dev->name, dev_data->phy_addr); in phy_xlnx_gem_marvell_alaska_cfg()
301 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
316 /* [6..5] 11 = Enable auto cross over detection */ in phy_xlnx_gem_marvell_alaska_cfg()
317 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
321 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
329 * eventually be changed from polling to interrupt-driven. in phy_xlnx_gem_marvell_alaska_cfg()
336 * -> all bits contained herein will be retained during the in phy_xlnx_gem_marvell_alaska_cfg()
342 * bit [11] = Auto-negotiation completed interrupt enable, in phy_xlnx_gem_marvell_alaska_cfg()
350 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
360 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
365 * auto-negotiation, then re-enable auto-negotiation. PHY link speed in phy_xlnx_gem_marvell_alaska_cfg()
366 * advertisement configuration as described in Zynq-7000 TRM, chapter in phy_xlnx_gem_marvell_alaska_cfg()
372 * auto-negotiation. This process involves: in phy_xlnx_gem_marvell_alaska_cfg()
375 * Copper Auto-Negotiation Advertisement Register, in phy_xlnx_gem_marvell_alaska_cfg()
377 * Copper Control Register, bit [15] = Reset -> apply all changes in phy_xlnx_gem_marvell_alaska_cfg()
380 * 1000BASE-T Control Register (if link speed = 1GBit/s), in phy_xlnx_gem_marvell_alaska_cfg()
382 * Copper Status Register, bit [5] = Copper Auto-Negotiation in phy_xlnx_gem_marvell_alaska_cfg()
393 if ((dev_data->phy_id & PHY_MRVL_PHY_ID_MODEL_MASK) == in phy_xlnx_gem_marvell_alaska_cfg()
405 phy_data_gbit = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
410 if (dev_conf->enable_fdx) { in phy_xlnx_gem_marvell_alaska_cfg()
411 if (dev_conf->max_link_speed == LINK_1GBIT) { in phy_xlnx_gem_marvell_alaska_cfg()
414 if (dev_conf->phy_advertise_lower) { in phy_xlnx_gem_marvell_alaska_cfg()
420 } else if (dev_conf->max_link_speed == LINK_100MBIT) { in phy_xlnx_gem_marvell_alaska_cfg()
423 if (dev_conf->phy_advertise_lower) { in phy_xlnx_gem_marvell_alaska_cfg()
427 } else if (dev_conf->max_link_speed == LINK_10MBIT) { in phy_xlnx_gem_marvell_alaska_cfg()
432 if (dev_conf->max_link_speed == LINK_1GBIT) { in phy_xlnx_gem_marvell_alaska_cfg()
435 if (dev_conf->phy_advertise_lower) { in phy_xlnx_gem_marvell_alaska_cfg()
441 } else if (dev_conf->max_link_speed == LINK_100MBIT) { in phy_xlnx_gem_marvell_alaska_cfg()
444 if (dev_conf->phy_advertise_lower) { in phy_xlnx_gem_marvell_alaska_cfg()
448 } else if (dev_conf->max_link_speed == LINK_10MBIT) { in phy_xlnx_gem_marvell_alaska_cfg()
454 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
456 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
461 * Afterwards, set the auto-negotiation enable bit [12] in the in phy_xlnx_gem_marvell_alaska_cfg()
465 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
468 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_cfg()
472 * Set the link speed to 'link down' for now, once auto-negotiation in phy_xlnx_gem_marvell_alaska_cfg()
475 dev_data->eff_link_speed = LINK_DOWN; in phy_xlnx_gem_marvell_alaska_cfg()
484 * events has occurred: auto-negotiation completed, link state
489 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_poll_sc()
490 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_marvell_alaska_poll_sc()
495 * PHY status change detection is implemented by reading the in phy_xlnx_gem_marvell_alaska_poll_sc()
500 * bit [11] = Auto-negotiation completed interrupt, in phy_xlnx_gem_marvell_alaska_poll_sc()
504 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_sc()
522 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_sc()
537 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_poll_lsts()
538 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_marvell_alaska_poll_lsts()
546 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_lsts()
562 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_marvell_alaska_poll_lspd()
563 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_marvell_alaska_poll_lspd()
572 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_marvell_alaska_poll_lspd()
600 * Vendor-specific PHY management functions for:
617 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_ti_dp83822_reset()
618 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_ti_dp83822_reset()
622 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_reset()
625 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_reset()
629 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_reset()
634 dev->name, dev_data->phy_addr); in phy_xlnx_gem_ti_dp83822_reset()
646 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_ti_dp83822_cfg()
647 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_ti_dp83822_cfg()
651 if (dev_conf->enable_fdx) { in phy_xlnx_gem_ti_dp83822_cfg()
652 if (dev_conf->max_link_speed == LINK_100MBIT) { in phy_xlnx_gem_ti_dp83822_cfg()
653 /* Advertise 100BASE-TX, full duplex */ in phy_xlnx_gem_ti_dp83822_cfg()
655 if (dev_conf->phy_advertise_lower) { in phy_xlnx_gem_ti_dp83822_cfg()
656 /* + 10BASE-TX, full duplex */ in phy_xlnx_gem_ti_dp83822_cfg()
659 } else if (dev_conf->max_link_speed == LINK_10MBIT) { in phy_xlnx_gem_ti_dp83822_cfg()
660 /* Advertise 10BASE-TX, full duplex */ in phy_xlnx_gem_ti_dp83822_cfg()
664 if (dev_conf->max_link_speed == LINK_100MBIT) { in phy_xlnx_gem_ti_dp83822_cfg()
665 /* Advertise 100BASE-TX, half duplex */ in phy_xlnx_gem_ti_dp83822_cfg()
667 if (dev_conf->phy_advertise_lower) { in phy_xlnx_gem_ti_dp83822_cfg()
668 /* + 10BASE-TX, half duplex */ in phy_xlnx_gem_ti_dp83822_cfg()
671 } else if (dev_conf->max_link_speed == LINK_10MBIT) { in phy_xlnx_gem_ti_dp83822_cfg()
672 /* Advertise 10BASE-TX, half duplex */ in phy_xlnx_gem_ti_dp83822_cfg()
676 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
679 /* Enable auto-negotiation */ in phy_xlnx_gem_ti_dp83822_cfg()
680 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
683 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
686 /* Robust Auto MDIX */ in phy_xlnx_gem_ti_dp83822_cfg()
687 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
690 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
693 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
695 /* Auto MDIX enable */ in phy_xlnx_gem_ti_dp83822_cfg()
701 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
707 phy_xlnx_gem_mdio_write(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_cfg()
711 * Set the link speed to 'link down' for now, once auto-negotiation in phy_xlnx_gem_ti_dp83822_cfg()
714 dev_data->eff_link_speed = LINK_DOWN; in phy_xlnx_gem_ti_dp83822_cfg()
723 * events has occurred: auto-negotiation completed, link state
728 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_ti_dp83822_poll_sc()
729 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_ti_dp83822_poll_sc()
740 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_sc()
768 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_ti_dp83822_poll_lsts()
769 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_ti_dp83822_poll_lsts()
773 * Double read of the BMSR is intentional - the relevant bit is latched in phy_xlnx_gem_ti_dp83822_poll_lsts()
774 * low so that after a link down -> link up transition, the first read in phy_xlnx_gem_ti_dp83822_poll_lsts()
778 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_lsts()
780 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_lsts()
796 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_ti_dp83822_poll_lspd()
797 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_ti_dp83822_poll_lspd()
801 phy_data = phy_xlnx_gem_mdio_read(dev_conf->base_addr, dev_data->phy_addr, in phy_xlnx_gem_ti_dp83822_poll_lspd()
846 * All vendor-specific API structs & code are located above
847 * -> assemble the top-level list of supported devices the
852 * @brief Top-level table of supported PHYs
853 * Top-level table of PHYs supported by the GEM driver. Contains 1..n
887 * @brief Top-level PHY detection function
888 * Top-level PHY detection function called by the GEM driver if PHY management
893 * @retval -ENOTSUP if PHY management is disabled for the current GEM
895 * @retval -EIO if no (supported) PHY was detected
900 const struct eth_xlnx_gem_dev_cfg *dev_conf = dev->config; in phy_xlnx_gem_detect()
901 struct eth_xlnx_gem_dev_data *dev_data = dev->data; in phy_xlnx_gem_detect()
904 uint8_t phy_first_addr = dev_conf->phy_mdio_addr_fix; in phy_xlnx_gem_detect()
905 uint8_t phy_last_addr = (dev_conf->phy_mdio_addr_fix != 0) ? in phy_xlnx_gem_detect()
906 dev_conf->phy_mdio_addr_fix : 31; in phy_xlnx_gem_detect()
912 * Clear the PHY address & ID in the device data struct -> may be in phy_xlnx_gem_detect()
913 * pre-initialized with a non-zero address meaning auto detection in phy_xlnx_gem_detect()
914 * is disabled. If eventually a supported PHY is found, a non- in phy_xlnx_gem_detect()
917 dev_data->phy_addr = 0; in phy_xlnx_gem_detect()
918 dev_data->phy_id = 0; in phy_xlnx_gem_detect()
919 dev_data->phy_access_api = NULL; in phy_xlnx_gem_detect()
921 if (!dev_conf->init_phy) { in phy_xlnx_gem_detect()
922 return -ENOTSUP; in phy_xlnx_gem_detect()
926 * PHY detection as described in Zynq-7000 TRM, chapter 16.3.4, in phy_xlnx_gem_detect()
932 /* Read the upper & lower PHY ID 16-bit words */ in phy_xlnx_gem_detect()
934 dev_conf->base_addr, phy_curr_addr, in phy_xlnx_gem_detect()
938 dev_conf->base_addr, phy_curr_addr, in phy_xlnx_gem_detect()
945 dev->name, in phy_xlnx_gem_detect()
949 * Iterate the list of all supported PHYs -> if the in phy_xlnx_gem_detect()
951 * in the device's run-time data struct. in phy_xlnx_gem_detect()
959 dev->name, in phy_xlnx_gem_detect()
965 * in the device's run-time data struct. in phy_xlnx_gem_detect()
967 dev_data->phy_addr = phy_curr_addr; in phy_xlnx_gem_detect()
968 dev_data->phy_id = phy_id; in phy_xlnx_gem_detect()
969 dev_data->phy_access_api = in phy_xlnx_gem_detect()
978 LOG_ERR("%s PHY detection failed", dev->name); in phy_xlnx_gem_detect()
979 return -EIO; in phy_xlnx_gem_detect()