57 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);  in phy_xlnx_gem_mdio_read()
58 	if (poll_cnt == 10) {  in phy_xlnx_gem_mdio_read()
90 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);  in phy_xlnx_gem_mdio_read()
91 	if (poll_cnt == 10) {  in phy_xlnx_gem_mdio_read()
136 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);  in phy_xlnx_gem_mdio_write()
137 	if (poll_cnt == 10) {  in phy_xlnx_gem_mdio_write()
171 	} while ((reg_val & ETH_XLNX_GEM_MDIO_IDLE_BIT) == 0 && poll_cnt < 10);  in phy_xlnx_gem_mdio_write()
172 	if (poll_cnt == 10) {  in phy_xlnx_gem_mdio_write()
216 	while (((phy_data & PHY_MRVL_COPPER_CONTROL_RESET_BIT) != 0) && (retries++ < 10)) {  in phy_xlnx_gem_marvell_alaska_reset()
220 	if (retries == 10) {  in phy_xlnx_gem_marvell_alaska_reset()
289 				(retries++ < 10)) {  in phy_xlnx_gem_marvell_alaska_cfg()
294 		if (retries == 10) {  in phy_xlnx_gem_marvell_alaska_cfg()
343 	 * bit [10] = Link status changed interrupt enable.  in phy_xlnx_gem_marvell_alaska_cfg()
415 				/* + 100 MBit/s, full duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
417 				/* + 10 MBit/s, full duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
421 			/* Advertise 100 MBit/s, full duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
424 				/* + 10 MBit/s, full duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
428 			/* Advertise 10 MBit/s, full duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
436 				/* + 100 MBit/s, half duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
438 				/* + 10 MBit/s, half duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
442 			/* Advertise 100 MBit/s, half duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
445 				/* + 10 MBit/s, half duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
449 			/* Advertise 10 MBit/s, half duplex */  in phy_xlnx_gem_marvell_alaska_cfg()
501 	 * bit [10] = Link status changed interrupt.  in phy_xlnx_gem_marvell_alaska_poll_sc()
628 	while (((phy_data & PHY_TI_BASIC_MODE_CONTROL_RESET_BIT) != 0) && (retries++ < 10)) {  in phy_xlnx_gem_ti_dp83822_reset()
632 	if (retries == 10) {  in phy_xlnx_gem_ti_dp83822_reset()
656 				/* + 10BASE-TX, full duplex */  in phy_xlnx_gem_ti_dp83822_cfg()
660 			/* Advertise 10BASE-TX, full duplex */  in phy_xlnx_gem_ti_dp83822_cfg()
668 				/* + 10BASE-TX, half duplex */  in phy_xlnx_gem_ti_dp83822_cfg()
672 			/* Advertise 10BASE-TX, half duplex */  in phy_xlnx_gem_ti_dp83822_cfg()
806 		/* PHYSCR[1] is the speed status bit: 0 = 100 Mbps, 1 = 10 Mbps. */  in phy_xlnx_gem_ti_dp83822_poll_lspd()