Lines Matching +full:reset +full:- +full:val
2 * DM8806 Stand-alone Ethernet PHY with RMII
6 * SPDX-License-Identifier: Apache-2.0
50 const struct phy_dm8806_config *cfg = drv_data->dev->config; in phy_dm8806_gpio_callback()
52 gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE); in phy_dm8806_gpio_callback()
53 k_sem_give(&drv_data->gpio_sem); in phy_dm8806_gpio_callback()
60 struct phy_dm8806_data *drv_data = dev->data; in phy_dm8806_thread_cb()
61 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_thread_cb()
63 if (drv_data->link_speed_chenge_cb != NULL) { in phy_dm8806_thread_cb()
64 drv_data->link_speed_chenge_cb(dev, state, cb_data); in phy_dm8806_thread_cb()
69 mdio_read(cfg->mdio, INT_STAT_PHY_ADDR, INT_STAT_REG_ADDR, &data); in phy_dm8806_thread_cb()
71 mdio_write(cfg->mdio, INT_STAT_PHY_ADDR, INT_STAT_REG_ADDR, data); in phy_dm8806_thread_cb()
72 gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE); in phy_dm8806_thread_cb()
82 k_sem_take(&drv_data->gpio_sem, K_FOREVER); in phy_dm8806_thread()
83 phy_dm8806_thread_cb(drv_data->dev, state, cb_data); in phy_dm8806_thread()
90 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_port_init()
92 res = gpio_pin_configure_dt(&cfg->gpio_rst, (GPIO_OUTPUT_INACTIVE | GPIO_PULL_UP)); in phy_dm8806_port_init()
94 LOG_ERR("Failed to configure gpio reset pin for PHY DM886 as an output"); in phy_dm8806_port_init()
97 /* Hardware reset of the PHY DM8806 */ in phy_dm8806_port_init()
98 gpio_pin_set_dt(&cfg->gpio_rst, true); in phy_dm8806_port_init()
100 LOG_ERR("Failed to assert gpio reset pin of the PHY DM886 to physical 0"); in phy_dm8806_port_init()
103 /* According to DM8806 datasheet (DM8806-DAVICOM.pdf), low active state on in phy_dm8806_port_init()
104 * the reset pin must remain minimum 10ms to perform hardware reset. in phy_dm8806_port_init()
107 res = gpio_pin_set_dt(&cfg->gpio_rst, false); in phy_dm8806_port_init()
109 LOG_ERR("Failed to assert gpio reset pin of the PHY DM886 to physical 1"); in phy_dm8806_port_init()
120 struct phy_dm8806_data *drv_data = dev->data; in phy_dm8806_init_interrupt()
121 void *cb_data = drv_data->cb_data; in phy_dm8806_init_interrupt()
122 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_init_interrupt()
128 res = mdio_read(cfg->mdio, INT_MASK_CTRL_PHY_ADDR, INT_MASK_CTRL_REG_ADDR, &data); in phy_dm8806_init_interrupt()
134 res = mdio_write(cfg->mdio, INT_MASK_CTRL_PHY_ADDR, INT_MASK_CTRL_REG_ADDR, data); in phy_dm8806_init_interrupt()
143 res = mdio_read(cfg->mdio, WOLL_CTRL_REG_PHY_ADDR, WOLL_CTRL_REG_REG_ADDR, &data); in phy_dm8806_init_interrupt()
149 res = mdio_write(cfg->mdio, WOLL_CTRL_REG_PHY_ADDR, WOLL_CTRL_REG_REG_ADDR, data); in phy_dm8806_init_interrupt()
159 if (device_is_ready(cfg->gpio_int.port) != true) { in phy_dm8806_init_interrupt()
161 return -ENODEV; in phy_dm8806_init_interrupt()
163 drv_data->dev = dev; in phy_dm8806_init_interrupt()
164 res = gpio_pin_configure_dt(&cfg->gpio_int, GPIO_INPUT); in phy_dm8806_init_interrupt()
172 gpio_init_callback(&drv_data->gpio_cb, phy_dm8806_gpio_callback, BIT(cfg->gpio_int.pin)); in phy_dm8806_init_interrupt()
173 res = gpio_add_callback(cfg->gpio_int.port, &drv_data->gpio_cb); in phy_dm8806_init_interrupt()
178 k_sem_init(&drv_data->gpio_sem, 0, K_SEM_MAX_LIMIT); in phy_dm8806_init_interrupt()
179 k_thread_create(&drv_data->thread, drv_data->thread_stack, in phy_dm8806_init_interrupt()
185 gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE); in phy_dm8806_init_interrupt()
198 uint16_t val; in phy_dm8806_init() local
199 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_init()
201 /* Configure reset pin for Davicom PHY DM8806 to be able to generate reset in phy_dm8806_init()
206 LOG_ERR("Failed to reset PHY DM8806 "); in phy_dm8806_init()
210 ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, &val); in phy_dm8806_init()
217 val |= (P5_50M_INT_CLK_SOURCE | P5_50M_CLK_OUT_ENABLE | P5_EN_FORCE); in phy_dm8806_init()
218 val &= (P5_SPEED_100M | P5_FULL_DUPLEX | P5_FORCE_LINK_ON); in phy_dm8806_init()
220 ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, PORT5_MAC_CONTROL, val); in phy_dm8806_init()
226 ret = mdio_read(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, &val); in phy_dm8806_init()
233 val &= LED_MODE_0; in phy_dm8806_init()
234 ret = mdio_write(cfg->mdio, PHY_ADDRESS_18H, IRQ_LED_CONTROL, val); in phy_dm8806_init()
255 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_get_link_state()
258 ret = mdio_read(cfg->mdio, 0x18, 0x18, &data); in phy_dm8806_get_link_state()
264 /* Read data from Switch Per-Port Register. */ in phy_dm8806_get_link_state()
265 ret = mdio_read(cfg->mdio, cfg->switch_addr, PORTX_SWITCH_STATUS, &data); in phy_dm8806_get_link_state()
267 LOG_ERR("Failes to read data drom DM8806 Switch Per-Port Registers area"); in phy_dm8806_get_link_state()
270 /* Extract speed and duplex status from Switch Per-Port Register: Per Port in phy_dm8806_get_link_state()
277 state->speed = LINK_HALF_10BASE_T; in phy_dm8806_get_link_state()
280 state->speed = LINK_FULL_10BASE_T; in phy_dm8806_get_link_state()
283 state->speed = LINK_HALF_100BASE_T; in phy_dm8806_get_link_state()
286 state->speed = LINK_FULL_100BASE_T; in phy_dm8806_get_link_state()
289 /* Extract link status from Switch Per-Port Register: Per Port Status Data in phy_dm8806_get_link_state()
294 state->is_up = true; in phy_dm8806_get_link_state()
296 state->is_up = false; in phy_dm8806_get_link_state()
306 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_cfg_link()
328 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
335 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
342 /* Turn off the auto-negotiation process. */ in phy_dm8806_cfg_link()
343 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
350 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
358 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
366 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
374 ret = mdio_read(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, &data); in phy_dm8806_cfg_link()
381 ret = mdio_write(cfg->mdio, cfg->phy_addr, PORTX_PHY_CONTROL_REGISTER, data); in phy_dm8806_cfg_link()
387 return -ENOTSUP; in phy_dm8806_cfg_link()
393 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_reg_read()
395 res = mdio_read(cfg->mdio, cfg->switch_addr, reg_addr, (uint16_t *)data); in phy_dm8806_reg_read()
406 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_reg_write()
408 res = mdio_write(cfg->mdio, cfg->switch_addr, reg_addr, data); in phy_dm8806_reg_write()
419 struct phy_dm8806_data *data = dev->data; in phy_dm8806_link_cb_set()
420 const struct phy_dm8806_config *cfg = dev->config; in phy_dm8806_link_cb_set()
422 res = gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_DISABLE); in phy_dm8806_link_cb_set()
427 data->link_speed_chenge_cb = cb; in phy_dm8806_link_cb_set()
428 data->cb_data = user_data; in phy_dm8806_link_cb_set()
429 gpio_pin_interrupt_configure_dt(&cfg->gpio_int, GPIO_INT_EDGE_TO_ACTIVE); in phy_dm8806_link_cb_set()