Lines Matching +full:reset +full:- +full:val
5 * SPDX-License-Identifier: Apache-2.0
23 /* PHYs out of reset check retry delay */
26 * Number of retries for PHYs out of reset check,
27 * rmii variants as ADIN11XX need 70ms maximum after hw reset to be up,
28 * so the increasing the count for that, as default 25ms (sw reset) + 45.
37 /* Software reset, CLK_25 disabled time*/
56 * - RM mask 0x6FFF
57 * - ADI driver example mask 0x2BFF
73 /* Software Power-down Control Register */
77 /* Software Power-down Status */
110 uint16_t *val) in phy_adin2111_c22_read() argument
112 const struct phy_adin2111_config *const cfg = dev->config; in phy_adin2111_c22_read()
114 return mdio_read(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_read()
118 uint16_t val) in phy_adin2111_c22_write() argument
120 const struct phy_adin2111_config *const cfg = dev->config; in phy_adin2111_c22_write()
122 return mdio_write(cfg->mdio, cfg->phy_addr, reg, val); in phy_adin2111_c22_write()
128 const struct phy_adin2111_config *cfg = dev->config; in phy_adin2111_c45_setup_dev_reg()
131 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad); in phy_adin2111_c45_setup_dev_reg()
135 rval = mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, reg); in phy_adin2111_c45_setup_dev_reg()
140 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS_CNTRL, devad | BIT(14)); in phy_adin2111_c45_setup_dev_reg()
144 uint16_t reg, uint16_t *val) in phy_adin2111_c45_read() argument
146 const struct phy_adin2111_config *cfg = dev->config; in phy_adin2111_c45_read()
149 if (cfg->mii) { in phy_adin2111_c45_read()
150 /* Using C22 -> devad bridge */ in phy_adin2111_c45_read()
156 return mdio_read(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_read()
159 return mdio_read_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_read()
163 uint16_t reg, uint16_t val) in phy_adin2111_c45_write() argument
165 const struct phy_adin2111_config *cfg = dev->config; in phy_adin2111_c45_write()
168 if (cfg->mii) { in phy_adin2111_c45_write()
169 /* Using C22 -> devad bridge */ in phy_adin2111_c45_write()
175 return mdio_write(cfg->mdio, cfg->phy_addr, ADIN1100_MMD_ACCESS, val); in phy_adin2111_c45_write()
178 return mdio_write_c45(cfg->mdio, cfg->phy_addr, devad, reg, val); in phy_adin2111_c45_write()
184 const struct phy_adin2111_config *cfg = dev->config; in phy_adin2111_reg_read()
187 mdio_bus_enable(cfg->mdio); in phy_adin2111_reg_read()
191 mdio_bus_disable(cfg->mdio); in phy_adin2111_reg_read()
199 const struct phy_adin2111_config *cfg = dev->config; in phy_adin2111_reg_write()
202 mdio_bus_enable(cfg->mdio); in phy_adin2111_reg_write()
206 mdio_bus_disable(cfg->mdio); in phy_adin2111_reg_write()
215 uint16_t val; in phy_adin2111_await_phy() local
218 * Port 2 PHY comes out of reset after Port 1 PHY, in phy_adin2111_await_phy()
219 * wait until both are out of reset. in phy_adin2111_await_phy()
221 * it comes out from reset. in phy_adin2111_await_phy()
225 ADIN2111_PHY_CRSM_IRQ_MASK, &val); in phy_adin2111_await_phy()
227 if (val != 0U) { in phy_adin2111_await_phy()
230 ret = -ETIMEDOUT; in phy_adin2111_await_phy()
240 struct phy_adin2111_data *const data = dev->data; in phy_adin2111_an_state_read()
254 data->state.is_up = !!(bmsr & MII_BMSR_LINK_STATUS); in phy_adin2111_an_state_read()
262 struct phy_adin2111_data *const data = dev->data; in phy_adin2111_handle_phy_irq()
275 return -EAGAIN; in phy_adin2111_handle_phy_irq()
278 k_sem_take(&data->sem, K_FOREVER); in phy_adin2111_handle_phy_irq()
282 memcpy(state, &data->state, sizeof(struct phy_link_state)); in phy_adin2111_handle_phy_irq()
284 k_sem_give(&data->sem); in phy_adin2111_handle_phy_irq()
294 uint16_t val; in phy_adin2111_sft_pd() local
305 ADIN2111_PHY_CRSM_STAT, &val); in phy_adin2111_sft_pd()
307 if ((val & ADIN2111_CRSM_STAT_CRSM_SFT_PD_RDY) == expected) { in phy_adin2111_sft_pd()
310 ret = -ETIMEDOUT; in phy_adin2111_sft_pd()
320 uint16_t val; in phy_adin2111_id() local
322 if (phy_adin2111_c22_read(dev, MII_PHYID1R, &val) < 0) { in phy_adin2111_id()
323 return -EIO; in phy_adin2111_id()
326 *phy_id = (val & UINT16_MAX) << 16; in phy_adin2111_id()
328 if (phy_adin2111_c22_read(dev, MII_PHYID2R, &val) < 0) { in phy_adin2111_id()
329 return -EIO; in phy_adin2111_id()
332 *phy_id |= (val & UINT16_MAX); in phy_adin2111_id()
340 struct phy_adin2111_data *const data = dev->data; in phy_adin2111_get_link_state()
342 k_sem_take(&data->sem, K_FOREVER); in phy_adin2111_get_link_state()
344 memcpy(state, &data->state, sizeof(struct phy_link_state)); in phy_adin2111_get_link_state()
346 k_sem_give(&data->sem); in phy_adin2111_get_link_state()
360 return -ENOTSUP; in phy_adin2111_cfg_link()
379 struct phy_adin2111_data *const data = dev->data; in invoke_link_cb()
382 if (data->cb == NULL) { in invoke_link_cb()
386 data->cb(dev, &state, data->cb_data); in invoke_link_cb()
391 struct phy_adin2111_data *const data = dev->data; in update_link_state()
392 const struct phy_adin2111_config *config = dev->config; in update_link_state()
402 old_state = data->state; in update_link_state()
403 data->state.is_up = !!(bmsr & MII_BMSR_LINK_STATUS); in update_link_state()
405 if (old_state.speed != data->state.speed || old_state.is_up != data->state.is_up) { in update_link_state()
407 LOG_INF("PHY (%d) Link is %s", config->phy_addr, data->state.is_up ? "up" : "down"); in update_link_state()
409 if (data->state.is_up == false) { in update_link_state()
415 LOG_INF("PHY (%d) Link speed %s Mb, %s duplex\n", config->phy_addr, in update_link_state()
416 (PHY_LINK_IS_SPEED_100M(data->state.speed) ? "100" : "10"), in update_link_state()
417 PHY_LINK_IS_FULL_DUPLEX(data->state.speed) ? "full" : "half"); in update_link_state()
428 const struct device *dev = data->dev; in monitor_work_handler()
431 k_sem_take(&data->sem, K_FOREVER); in monitor_work_handler()
435 k_sem_give(&data->sem); in monitor_work_handler()
438 k_work_reschedule(&data->monitor_work, K_MSEC(CONFIG_PHY_MONITOR_PERIOD)); in monitor_work_handler()
443 const struct phy_adin2111_config *const cfg = dev->config; in phy_adin2111_init()
444 struct phy_adin2111_data *const data = dev->data; in phy_adin2111_init()
446 uint16_t val; in phy_adin2111_init() local
450 data->dev = dev; in phy_adin2111_init()
451 data->state.is_up = false; in phy_adin2111_init()
452 data->state.speed = LINK_FULL_10BASE_T; in phy_adin2111_init()
456 * reset may not be performed from the mac layer, doing a clean reset here. in phy_adin2111_init()
458 if (cfg->mii) { in phy_adin2111_init()
467 LOG_ERR("PHY %u didn't come out of reset, %d", in phy_adin2111_init()
468 cfg->phy_addr, ret); in phy_adin2111_init()
469 return -ENODEV; in phy_adin2111_init()
475 cfg->phy_addr, ret); in phy_adin2111_init()
476 return -ENODEV; in phy_adin2111_init()
480 LOG_ERR("PHY %u unexpected PHY ID %X", cfg->phy_addr, phy_id); in phy_adin2111_init()
481 return -EINVAL; in phy_adin2111_init()
484 LOG_INF("PHY %u ID %X", cfg->phy_addr, phy_id); in phy_adin2111_init()
509 ADIN2111_PHY_CRSM_IRQ_STATUS, &val); in phy_adin2111_init()
514 if (val & ADIN2111_PHY_CRSM_IRQ_STATUS_FATAL_ERR) { in phy_adin2111_init()
515 LOG_ERR("PHY %u CRSM reports fatal system error", cfg->phy_addr); in phy_adin2111_init()
516 return -ENODEV; in phy_adin2111_init()
520 ADIN2111_PHY_SUBSYS_IRQ_STATUS, &val); in phy_adin2111_init()
525 if (!cfg->led0_en || !cfg->led1_en) { in phy_adin2111_init()
527 ADIN2111_PHY_LED_CNTRL, &val); in phy_adin2111_init()
531 if (!cfg->led0_en) { in phy_adin2111_init()
532 val &= ~(ADIN2111_PHY_LED_CNTRL_LED0_EN); in phy_adin2111_init()
534 if (!cfg->led1_en) { in phy_adin2111_init()
535 val &= ~(ADIN2111_PHY_LED_CNTRL_LED1_EN); in phy_adin2111_init()
538 ADIN2111_PHY_LED_CNTRL, val); in phy_adin2111_init()
545 ret = phy_adin2111_c45_read(dev, MDIO_MMD_PMAPMD, MDIO_PMA_B10L_STAT, &val); in phy_adin2111_init()
550 tx_24v_supported = !!(val & MDIO_PMA_B10L_STAT_2V4_ABLE); in phy_adin2111_init()
552 LOG_INF("PHY %u 2.4V mode %s", cfg->phy_addr, in phy_adin2111_init()
555 if (!cfg->tx_24v & tx_24v_supported) { in phy_adin2111_init()
557 cfg->phy_addr); in phy_adin2111_init()
560 /* config 2.4V auto-negotiation */ in phy_adin2111_init()
561 ret = phy_adin2111_c45_read(dev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, &val); in phy_adin2111_init()
567 val |= MDIO_AN_T1_ADV_H_10L_TX_HI; in phy_adin2111_init()
569 val &= ~MDIO_AN_T1_ADV_H_10L_TX_HI; in phy_adin2111_init()
572 if (cfg->tx_24v) { in phy_adin2111_init()
575 cfg->phy_addr); in phy_adin2111_init()
576 return -EINVAL; in phy_adin2111_init()
579 val |= MDIO_AN_T1_ADV_H_10L_TX_HI_REQ; in phy_adin2111_init()
581 val &= ~MDIO_AN_T1_ADV_H_10L_TX_HI_REQ; in phy_adin2111_init()
584 ret = phy_adin2111_c45_write(dev, MDIO_MMD_AN, MDIO_AN_T1_ADV_H, val); in phy_adin2111_init()
589 /* enable auto-negotiation */ in phy_adin2111_init()
596 if (cfg->mii) { in phy_adin2111_init()
597 k_work_init_delayable(&data->monitor_work, monitor_work_handler); in phy_adin2111_init()
598 monitor_work_handler(&data->monitor_work.work); in phy_adin2111_init()
612 struct phy_adin2111_data *const data = dev->data; in phy_adin2111_link_cb_set()
614 data->cb = cb; in phy_adin2111_link_cb_set()
615 data->cb_data = user_data; in phy_adin2111_link_cb_set()