Lines Matching +full:tx +full:- +full:sync +full:- +full:mode
7 * SPDX-License-Identifier: Apache-2.0
22 #define ETH_XLNX_BUFFER_ALIGNMENT 4 /* RX/TX buffer alignment (in bytes) */
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
56 * [13] FCS status bit for FCS ignore mode
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
83 * [30] Wrap bit, last BD in TX BD ring
85 * [27] TX frame corruption due to AHB/AXI error, HRESP errors or buffers
86 * exhausted mid-frame
87 * [26] Late collision, TX error detected
90 * [15] Last buffer bit, indicates end of current TX frame
116 * Zynq-7000 TX clock configuration:
129 * UltraScale TX clock configuration: comp.
130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
156 * TXSR = gem.tx_status TX Status register
218 * [06] Increment statistics registers - for testing purposes only
223 * [01] Local loopback mode
241 * [29] Disable rejection of non-standard preamble
243 * [27] Enable SGMII mode
245 * [25] Enable frames to be received in HDX mode while transmitting
253 * [13] Enable pause TX upon 802.3 pause frame reception
254 * [12] Retry test - for testing purposes only
256 * [10] Gigabit mode enable
262 * [04] Copy all frames = promiscuous mode
263 * [02] Discard non-VLAN frames enable
265 * [00] Speed selection: 1 = 100Mbit/s, 0 = 10 Mbit/s, GBE mode is
303 * [11] Enable/disable TCP|UDP/IP TX checksum offload
304 * [10] TX buffer half/full memory size
327 * [21] PTP sync frame transmitted
329 * [19] PTP sync frame received
332 * [16] Auto-negotiation completed
336 * [12] Pause frame received with non-zero pause quantum
344 * [03] Set 'used' bit in TX BD encountered
395 * [15 .. 00] 16-bit data word
447 (ETH_XLNX_BUFFER_ALIGNMENT-1)) & ~(ETH_XLNX_BUFFER_ALIGNMENT-1)),\
449 (ETH_XLNX_BUFFER_ALIGNMENT-1)) & ~(ETH_XLNX_BUFFER_ALIGNMENT-1)),\
477 /* Device run-time data declaration macro */
498 + (ETH_XLNX_BUFFER_ALIGNMENT - 1))\
499 & ~(ETH_XLNX_BUFFER_ALIGNMENT - 1))];\
503 + (ETH_XLNX_BUFFER_ALIGNMENT - 1))\
504 & ~(ETH_XLNX_BUFFER_ALIGNMENT - 1))];\
522 /* RX/TX BD Ring initialization macro */
524 if (dev_conf->base_addr == DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0)) {\
525 dev_data->rxbd_ring.first_bd = &(eth_xlnx_gem##port##_dma_area.rx_bd[0]);\
526 dev_data->txbd_ring.first_bd = &(eth_xlnx_gem##port##_dma_area.tx_bd[0]);\
527 dev_data->first_rx_buffer = (uint8_t *)eth_xlnx_gem##port##_dma_area.rx_buffer;\
528 dev_data->first_tx_buffer = (uint8_t *)eth_xlnx_gem##port##_dma_area.tx_buffer;\
531 /* Top-level device initialization macro - bundles all of the above */
578 * cpu_1x clock (Zynq-7000) or the LPD LSBUS clock (UltraScale).
588 /* Dividers > 48 are only available in the Zynq-7000 */
619 /* The values of this enum are one-hot encoded */
630 * An array of these descriptors for each RX and TX is used to
632 * points to the start of a RX or TX buffer within the DMA memory
637 /* TODO for Cortex-A53: 64-bit addressing */
641 /* Buffer control word (different contents for RX and TX) */
649 * is used to manage either the RX or TX buffer descriptor array
652 * last descriptor's control word has a special last-in-ring bit set).
656 * or evaluated for the next RX/TX operation.
663 /* Index of the next BD to be used for TX */
665 /* Index of the next BD to be processed (both RX/TX) */
679 * to clock sources, is specific to either the Zynq-7000 or the
736 * @brief Run-time device configuration data structure.
739 * controller instance which is modifyable at run-time, such as