Lines Matching +full:start +full:- +full:from +full:- +full:bottom
7 * SPDX-License-Identifier: Apache-2.0
26 /* Receive Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-2. */
30 * [31 .. 02] Mask for effective buffer address -> excludes [1..0]
47 * [23 .. 22] These bits have different semantics depending on whether RX check-
54 * [15] End-of-frame bit
55 * [14] Start-of-frame bit
78 /* Transmit Buffer Descriptor bits & masks: comp. Zynq-7000 TRM, Table 16-3. */
86 * exhausted mid-frame
116 * Zynq-7000 TX clock configuration:
130 * https://www.xilinx.com/html_docs/registers/ug1087/ug1087-zynq-ultrascale-registers.html
165 * LADDR1L = gem.spec_addr1_bot Specific address 1 bottom register
167 * LADDR2L = gem.spec_addr2_bot Specific address 2 bottom register
169 * LADDR3L = gem.spec_addr3_bot Specific address 3 bottom register
171 * LADDR4L = gem.spec_addr4_bot Specific address 4 bottom register
216 * [09] Start transmission (tx_go)
218 * [06] Increment statistics registers - for testing purposes only
241 * [29] Disable rejection of non-standard preamble
250 * [17] Discard FCS from received frames
254 * [12] Retry test - for testing purposes only
263 * [02] Discard non-VLAN frames enable
332 * [16] Auto-negotiation completed
336 * [12] Pause frame received with non-zero pause quantum
395 * [15 .. 00] 16-bit data word
447 (ETH_XLNX_BUFFER_ALIGNMENT-1)) & ~(ETH_XLNX_BUFFER_ALIGNMENT-1)),\
449 (ETH_XLNX_BUFFER_ALIGNMENT-1)) & ~(ETH_XLNX_BUFFER_ALIGNMENT-1)),\
477 /* Device run-time data declaration macro */
498 + (ETH_XLNX_BUFFER_ALIGNMENT - 1))\
499 & ~(ETH_XLNX_BUFFER_ALIGNMENT - 1))];\
503 + (ETH_XLNX_BUFFER_ALIGNMENT - 1))\
504 & ~(ETH_XLNX_BUFFER_ALIGNMENT - 1))];\
524 if (dev_conf->base_addr == DT_REG_ADDR_BY_IDX(DT_INST(port, xlnx_gem), 0)) {\
525 dev_data->rxbd_ring.first_bd = &(eth_xlnx_gem##port##_dma_area.rx_bd[0]);\
526 dev_data->txbd_ring.first_bd = &(eth_xlnx_gem##port##_dma_area.tx_bd[0]);\
527 dev_data->first_rx_buffer = (uint8_t *)eth_xlnx_gem##port##_dma_area.rx_buffer;\
528 dev_data->first_tx_buffer = (uint8_t *)eth_xlnx_gem##port##_dma_area.tx_buffer;\
531 /* Top-level device initialization macro - bundles all of the above */
577 * used to generate the MDIO interface clock (MDC) from either the
578 * cpu_1x clock (Zynq-7000) or the LPD LSBUS clock (UltraScale).
588 /* Dividers > 48 are only available in the Zynq-7000 */
619 /* The values of this enum are one-hot encoded */
632 * points to the start of a RX or TX buffer within the DMA memory
637 /* TODO for Cortex-A53: 64-bit addressing */
650 * (while the buffer descriptors are just an array from the software
652 * last descriptor's control word has a special last-in-ring bit set).
653 * It contains a pointer to the start of the descriptor array, a
676 * either acquired from the generated header file based on the
677 * data from Kconfig, or from header file based on the device tree
679 * to clock sources, is specific to either the Zynq-7000 or the
736 * @brief Run-time device configuration data structure.
739 * controller instance which is modifyable at run-time, such as