Lines Matching +full:underflow +full:- +full:control
5 * SPDX-License-Identifier: Apache-2.0
73 #define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->DESC3 & \
86 #define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->Status & \
161 size_t index = (RxBufferPtr)buff - &dma_rx_buffer[0]; in HAL_ETH_RxLinkCallback()
166 header->size = Length; in HAL_ETH_RxLinkCallback()
175 ((struct eth_stm32_rx_buffer_header *)*pEnd)->next = header; in HAL_ETH_RxLinkCallback()
188 &dma_tx_buffer_header[ctx->first_tx_buffer_index]; in HAL_ETH_TxFreeCallback()
191 buffer_header->used = false; in HAL_ETH_TxFreeCallback()
192 if (buffer_header->tx_buff.next != NULL) { in HAL_ETH_TxFreeCallback()
193 buffer_header = CONTAINER_OF(buffer_header->tx_buff.next, in HAL_ETH_TxFreeCallback()
199 ctx->used = false; in HAL_ETH_TxFreeCallback()
273 uint32_t tmp = heth->Instance->MACFFR; in setup_mac_filter()
289 heth->Instance->MACFFR = tmp; in setup_mac_filter()
294 tmp = heth->Instance->MACFFR; in setup_mac_filter()
296 heth->Instance->MACFFR = tmp; in setup_mac_filter()
303 if (ntohs(NET_ETH_HDR(pkt)->type) != NET_ETH_PTYPE_PTP) { in eth_is_ptp_pkt()
316 ctx->pkt->timestamp.second = timestamp->TimeStampHigh; in HAL_ETH_TxPtpCallback()
317 ctx->pkt->timestamp.nanosecond = timestamp->TimeStampLow; in HAL_ETH_TxPtpCallback()
319 net_if_add_tx_timestamp(ctx->pkt); in HAL_ETH_TxPtpCallback()
326 struct eth_stm32_hal_dev_data *dev_data = dev->data; in eth_tx()
344 __ASSERT_NO_MSG(pkt->frags != NULL); in eth_tx()
348 heth = &dev_data->heth; in eth_tx()
353 return -EIO; in eth_tx()
356 k_mutex_lock(&dev_data->tx_mutex, K_FOREVER); in eth_tx()
360 buf_header = &dma_tx_buffer_header[ctx->first_tx_buffer_index]; in eth_tx()
362 dma_tx_desc = heth->TxDesc; in eth_tx()
376 dma_tx_desc->Status |= ETH_DMATXDESC_TTSE; in eth_tx()
385 if (net_pkt_read(pkt, buf_header->tx_buff.buffer, ETH_STM32_TX_BUF_SIZE)) { in eth_tx()
386 res = -ENOBUFS; in eth_tx()
391 buf_header->tx_buff.len = ETH_STM32_TX_BUF_SIZE; in eth_tx()
393 buf_header->tx_buff.next = &dma_tx_buffer_header[next_buffer_id].tx_buff; in eth_tx()
396 remaining_read -= ETH_STM32_TX_BUF_SIZE; in eth_tx()
398 if (net_pkt_read(pkt, buf_header->tx_buff.buffer, remaining_read)) { in eth_tx()
399 res = -ENOBUFS; in eth_tx()
402 buf_header->tx_buff.len = remaining_read; in eth_tx()
403 buf_header->tx_buff.next = NULL; in eth_tx()
406 dma_buffer = (uint8_t *)(dma_tx_desc->Buffer1Addr); in eth_tx()
409 res = -ENOBUFS; in eth_tx()
417 tx_config.TxBuffer = &dma_tx_buffer_header[ctx->first_tx_buffer_index].tx_buff; in eth_tx()
420 k_sem_reset(&dev_data->tx_int_sem); in eth_tx()
429 res = -EIO; in eth_tx()
439 if (k_sem_take(&dev_data->tx_int_sem, in eth_tx()
443 res = -EIO; in eth_tx()
481 res = -EIO; in eth_tx()
485 /* When Transmit Underflow flag is set, clear it and issue a in eth_tx()
488 if ((heth->Instance->DMASR & ETH_DMASR_TUS) != (uint32_t)RESET) { in eth_tx()
490 heth->Instance->DMASR = ETH_DMASR_TUS; in eth_tx()
492 heth->Instance->DMATPDR = 0; in eth_tx()
493 res = -EIO; in eth_tx()
503 while (!(last_dma_tx_desc->Status & ETH_DMATXDESC_LS) && in eth_tx()
504 last_dma_tx_desc->Buffer2NextDescAddr) { in eth_tx()
506 (ETH_DMADescTypeDef *)last_dma_tx_desc->Buffer2NextDescAddr; in eth_tx()
514 if (last_dma_tx_desc->Status & ETH_DMATXDESC_LS && in eth_tx()
515 last_dma_tx_desc->Status & ETH_DMATXDESC_TTSS) { in eth_tx()
516 pkt->timestamp.second = last_dma_tx_desc->TimeStampHigh; in eth_tx()
517 pkt->timestamp.nanosecond = last_dma_tx_desc->TimeStampLow; in eth_tx()
520 pkt->timestamp.second = UINT64_MAX; in eth_tx()
521 pkt->timestamp.nanosecond = UINT32_MAX; in eth_tx()
540 k_mutex_unlock(&dev_data->tx_mutex); in eth_tx()
547 return ctx->iface; in get_iface()
576 dev_data = dev->data; in eth_rx()
580 heth = &dev_data->heth; in eth_rx()
590 rx_header; rx_header = rx_header->next) { in eth_rx()
591 total_len += rx_header->size; in eth_rx()
600 total_len = heth->RxFrameInfos.length; in eth_rx()
601 dma_buffer = (uint8_t *)heth->RxFrameInfos.buffer; in eth_rx()
614 last_dma_rx_desc = heth->RxFrameInfos.LSRxDesc; in eth_rx()
615 if (last_dma_rx_desc->TimeStampHigh != UINT32_MAX || in eth_rx()
616 last_dma_rx_desc->TimeStampLow != UINT32_MAX) { in eth_rx()
617 timestamp.second = last_dma_rx_desc->TimeStampHigh; in eth_rx()
618 timestamp.nanosecond = last_dma_rx_desc->TimeStampLow; in eth_rx()
632 rx_header; rx_header = rx_header->next) { in eth_rx()
633 const size_t index = rx_header - &dma_rx_buffer_header[0]; in eth_rx()
636 if (net_pkt_write(pkt, dma_rx_buffer[index], rx_header->size)) { in eth_rx()
655 rx_header; rx_header = rx_header->next) { in eth_rx()
656 rx_header->used = false; in eth_rx()
661 dma_rx_desc = heth->RxFrameInfos.FSRxDesc; in eth_rx()
663 for (int i = 0; i < heth->RxFrameInfos.SegCount; i++) { in eth_rx()
664 dma_rx_desc->Status |= ETH_DMARXDESC_OWN; in eth_rx()
666 (dma_rx_desc->Buffer2NextDescAddr); in eth_rx()
670 heth->RxFrameInfos.SegCount = 0; in eth_rx()
675 if ((heth->Instance->DMASR & ETH_DMASR_RBUS) != (uint32_t)RESET) { in eth_rx()
677 heth->Instance->DMASR = ETH_DMASR_RBUS; in eth_rx()
679 heth->Instance->DMARPDR = 0; in eth_rx()
688 pkt->timestamp.second = timestamp.second; in eth_rx()
689 pkt->timestamp.nanosecond = timestamp.nanosecond; in eth_rx()
718 dev_data = dev->data; in rx_thread()
723 res = k_sem_take(&dev_data->rx_int_sem, in rx_thread()
727 if (dev_data->link_up != true) { in rx_thread()
728 dev_data->link_up = true; in rx_thread()
745 } else if (res == -EAGAIN) { in rx_thread()
747 hal_ret = read_eth_phy_register(&dev_data->heth, in rx_thread()
751 if (dev_data->link_up != true) { in rx_thread()
752 dev_data->link_up = true; in rx_thread()
757 if (dev_data->link_up != false) { in rx_thread()
758 dev_data->link_up = false; in rx_thread()
775 dev_data = dev->data; in eth_isr()
779 heth = &dev_data->heth; in eth_isr()
795 k_sem_give(&dev_data->tx_int_sem); in HAL_ETH_TxCpltCallback()
826 eth_stats_update_errors_rx(dev_data->iface); in HAL_ETH_ErrorCallback()
830 eth_stats_update_errors_tx(dev_data->iface); in HAL_ETH_ErrorCallback()
836 eth_stats_update_errors_rx(dev_data->iface); in HAL_ETH_ErrorCallback()
841 eth_stats_update_errors_tx(dev_data->iface); in HAL_ETH_ErrorCallback()
851 eth_stats_update_errors_rx(dev_data->iface); in HAL_ETH_ErrorCallback()
860 eth_stats_update_errors_tx(dev_data->iface); in HAL_ETH_ErrorCallback()
867 dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRCRCEPR; in HAL_ETH_ErrorCallback()
868 dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRAEPR; in HAL_ETH_ErrorCallback()
870 dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRFCECR; in HAL_ETH_ErrorCallback()
871 dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRFAECR; in HAL_ETH_ErrorCallback()
887 k_sem_give(&dev_data->rx_int_sem); in HAL_ETH_RxCpltCallback()
893 /* "zephyr,random-mac-address" is set, generate a random mac address */ in generate_mac()
926 dev_data = dev->data; in eth_initialize()
927 cfg = dev->config; in eth_initialize()
932 dev_data->clock = DEVICE_DT_GET(STM32_CLOCK_CONTROL_NODE); in eth_initialize()
934 if (!device_is_ready(dev_data->clock)) { in eth_initialize()
935 LOG_ERR("clock control device not ready"); in eth_initialize()
936 return -ENODEV; in eth_initialize()
940 ret = clock_control_on(dev_data->clock, in eth_initialize()
941 (clock_control_subsys_t)&cfg->pclken); in eth_initialize()
942 ret |= clock_control_on(dev_data->clock, in eth_initialize()
943 (clock_control_subsys_t)&cfg->pclken_tx); in eth_initialize()
944 ret |= clock_control_on(dev_data->clock, in eth_initialize()
945 (clock_control_subsys_t)&cfg->pclken_rx); in eth_initialize()
947 ret |= clock_control_on(dev_data->clock, in eth_initialize()
948 (clock_control_subsys_t)&cfg->pclken_ptp); in eth_initialize()
953 return -EIO; in eth_initialize()
957 ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT); in eth_initialize()
963 heth = &dev_data->heth; in eth_initialize()
965 generate_mac(dev_data->mac_addr); in eth_initialize()
967 heth->Init.MACAddr = dev_data->mac_addr; in eth_initialize()
970 heth->Init.TxDesc = dma_tx_desc_tab; in eth_initialize()
971 heth->Init.RxDesc = dma_rx_desc_tab; in eth_initialize()
972 heth->Init.RxBuffLen = ETH_STM32_RX_BUF_SIZE; in eth_initialize()
983 return -EINVAL; in eth_initialize()
991 heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL; in eth_initialize()
993 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE; in eth_initialize()
1007 dev_data->link_up = false; in eth_initialize()
1010 k_mutex_init(&dev_data->tx_mutex); in eth_initialize()
1011 k_sem_init(&dev_data->rx_int_sem, 0, K_SEM_MAX_LIMIT); in eth_initialize()
1013 k_sem_init(&dev_data->tx_int_sem, 0, K_SEM_MAX_LIMIT); in eth_initialize()
1060 dev_data->mac_addr[0], dev_data->mac_addr[1], in eth_initialize()
1061 dev_data->mac_addr[2], dev_data->mac_addr[3], in eth_initialize()
1062 dev_data->mac_addr[4], dev_data->mac_addr[5]); in eth_initialize()
1070 struct eth_stm32_hal_dev_data *dev_data = (struct eth_stm32_hal_dev_data *)dev->data; in eth_stm32_mcast_filter()
1076 heth = &dev_data->heth; in eth_stm32_mcast_filter()
1078 crc = __RBIT(crc32_ieee(filter->mac_address.addr, sizeof(struct net_eth_addr))); in eth_stm32_mcast_filter()
1081 __ASSERT_NO_MSG(hash_index < ARRAY_SIZE(dev_data->hash_index_cnt)); in eth_stm32_mcast_filter()
1084 hash_table[0] = heth->Instance->MACHT0R; in eth_stm32_mcast_filter()
1085 hash_table[1] = heth->Instance->MACHT1R; in eth_stm32_mcast_filter()
1087 hash_table[0] = heth->Instance->MACHTLR; in eth_stm32_mcast_filter()
1088 hash_table[1] = heth->Instance->MACHTHR; in eth_stm32_mcast_filter()
1091 if (filter->set) { in eth_stm32_mcast_filter()
1092 dev_data->hash_index_cnt[hash_index]++; in eth_stm32_mcast_filter()
1095 if (dev_data->hash_index_cnt[hash_index] == 0) { in eth_stm32_mcast_filter()
1100 dev_data->hash_index_cnt[hash_index]--; in eth_stm32_mcast_filter()
1101 if (dev_data->hash_index_cnt[hash_index] == 0) { in eth_stm32_mcast_filter()
1107 heth->Instance->MACHT0R = hash_table[0]; in eth_stm32_mcast_filter()
1108 heth->Instance->MACHT1R = hash_table[1]; in eth_stm32_mcast_filter()
1110 heth->Instance->MACHTLR = hash_table[0]; in eth_stm32_mcast_filter()
1111 heth->Instance->MACHTHR = hash_table[1]; in eth_stm32_mcast_filter()
1128 dev_data = dev->data; in eth_iface_init()
1131 if (dev_data->iface == NULL) { in eth_iface_init()
1132 dev_data->iface = iface; in eth_iface_init()
1137 net_if_set_link_addr(iface, dev_data->mac_addr, in eth_iface_init()
1138 sizeof(dev_data->mac_addr), in eth_iface_init()
1152 const struct eth_stm32_hal_dev_cfg *cfg = dev->config; in eth_iface_init()
1154 __ASSERT_NO_MSG(cfg->config_func != NULL); in eth_iface_init()
1155 cfg->config_func(); in eth_iface_init()
1157 /* Start interruption-poll thread */ in eth_iface_init()
1158 k_thread_create(&dev_data->rx_thread, dev_data->rx_thread_stack, in eth_iface_init()
1159 K_KERNEL_STACK_SIZEOF(dev_data->rx_thread_stack), in eth_iface_init()
1166 k_thread_name_set(&dev_data->rx_thread, "stm_eth"); in eth_iface_init()
1204 int ret = -ENOTSUP; in eth_stm32_hal_set_config()
1208 dev_data = dev->data; in eth_stm32_hal_set_config()
1209 heth = &dev_data->heth; in eth_stm32_hal_set_config()
1213 memcpy(dev_data->mac_addr, config->mac_address.addr, 6); in eth_stm32_hal_set_config()
1214 heth->Instance->MACA0HR = (dev_data->mac_addr[5] << 8) | in eth_stm32_hal_set_config()
1215 dev_data->mac_addr[4]; in eth_stm32_hal_set_config()
1216 heth->Instance->MACA0LR = (dev_data->mac_addr[3] << 24) | in eth_stm32_hal_set_config()
1217 (dev_data->mac_addr[2] << 16) | in eth_stm32_hal_set_config()
1218 (dev_data->mac_addr[1] << 8) | in eth_stm32_hal_set_config()
1219 dev_data->mac_addr[0]; in eth_stm32_hal_set_config()
1220 net_if_set_link_addr(dev_data->iface, dev_data->mac_addr, in eth_stm32_hal_set_config()
1221 sizeof(dev_data->mac_addr), in eth_stm32_hal_set_config()
1228 if (config->promisc_mode) { in eth_stm32_hal_set_config()
1229 heth->Instance->MACPFR |= ETH_MACPFR_PR; in eth_stm32_hal_set_config()
1231 heth->Instance->MACPFR &= ~ETH_MACPFR_PR; in eth_stm32_hal_set_config()
1234 if (config->promisc_mode) { in eth_stm32_hal_set_config()
1235 heth->Instance->MACFFR |= ETH_MACFFR_PM; in eth_stm32_hal_set_config()
1237 heth->Instance->MACFFR &= ~ETH_MACFFR_PM; in eth_stm32_hal_set_config()
1245 eth_stm32_mcast_filter(dev, &config->filter); in eth_stm32_hal_set_config()
1258 struct eth_stm32_hal_dev_data *dev_data = dev->data; in eth_stm32_get_ptp_clock()
1260 return dev_data->ptp_clock; in eth_stm32_get_ptp_clock()
1267 struct eth_stm32_hal_dev_data *dev_data = dev->data; in eth_stm32_hal_get_stats()
1269 return &dev_data->stats; in eth_stm32_hal_get_stats()
1354 struct ptp_context *ptp_context = dev->data; in ptp_clock_stm32_set()
1355 struct eth_stm32_hal_dev_data *eth_dev_data = ptp_context->eth_dev_data; in ptp_clock_stm32_set()
1356 ETH_HandleTypeDef *heth = ð_dev_data->heth; in ptp_clock_stm32_set()
1362 heth->Instance->MACSTSUR = tm->second; in ptp_clock_stm32_set()
1363 heth->Instance->MACSTNUR = tm->nanosecond; in ptp_clock_stm32_set()
1364 heth->Instance->MACTSCR |= ETH_MACTSCR_TSINIT; in ptp_clock_stm32_set()
1365 while (heth->Instance->MACTSCR & ETH_MACTSCR_TSINIT_Msk) { in ptp_clock_stm32_set()
1369 heth->Instance->PTPTSHUR = tm->second; in ptp_clock_stm32_set()
1370 heth->Instance->PTPTSLUR = tm->nanosecond; in ptp_clock_stm32_set()
1371 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSTI; in ptp_clock_stm32_set()
1372 while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSSTI_Msk) { in ptp_clock_stm32_set()
1385 struct ptp_context *ptp_context = dev->data; in ptp_clock_stm32_get()
1386 struct eth_stm32_hal_dev_data *eth_dev_data = ptp_context->eth_dev_data; in ptp_clock_stm32_get()
1387 ETH_HandleTypeDef *heth = ð_dev_data->heth; in ptp_clock_stm32_get()
1394 tm->second = heth->Instance->MACSTSR; in ptp_clock_stm32_get()
1395 tm->nanosecond = heth->Instance->MACSTNR; in ptp_clock_stm32_get()
1396 second_2 = heth->Instance->MACSTSR; in ptp_clock_stm32_get()
1398 tm->second = heth->Instance->PTPTSHR; in ptp_clock_stm32_get()
1399 tm->nanosecond = heth->Instance->PTPTSLR; in ptp_clock_stm32_get()
1400 second_2 = heth->Instance->PTPTSHR; in ptp_clock_stm32_get()
1405 if (tm->second != second_2 && tm->nanosecond < NSEC_PER_SEC / 2) { in ptp_clock_stm32_get()
1410 tm->second = second_2; in ptp_clock_stm32_get()
1418 struct ptp_context *ptp_context = dev->data; in ptp_clock_stm32_adjust()
1419 struct eth_stm32_hal_dev_data *eth_dev_data = ptp_context->eth_dev_data; in ptp_clock_stm32_adjust()
1420 ETH_HandleTypeDef *heth = ð_dev_data->heth; in ptp_clock_stm32_adjust()
1423 if ((increment <= (int32_t)(-NSEC_PER_SEC)) || in ptp_clock_stm32_adjust()
1425 ret = -EINVAL; in ptp_clock_stm32_adjust()
1430 heth->Instance->MACSTSUR = 0; in ptp_clock_stm32_adjust()
1432 heth->Instance->MACSTNUR = increment; in ptp_clock_stm32_adjust()
1434 heth->Instance->MACSTNUR = ETH_MACSTNUR_ADDSUB | (NSEC_PER_SEC + increment); in ptp_clock_stm32_adjust()
1436 heth->Instance->MACTSCR |= ETH_MACTSCR_TSUPDT; in ptp_clock_stm32_adjust()
1437 while (heth->Instance->MACTSCR & ETH_MACTSCR_TSUPDT_Msk) { in ptp_clock_stm32_adjust()
1441 heth->Instance->PTPTSHUR = 0; in ptp_clock_stm32_adjust()
1443 heth->Instance->PTPTSLUR = increment; in ptp_clock_stm32_adjust()
1445 heth->Instance->PTPTSLUR = ETH_PTPTSLUR_TSUPNS | (-increment); in ptp_clock_stm32_adjust()
1447 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSTU; in ptp_clock_stm32_adjust()
1448 while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSSTU_Msk) { in ptp_clock_stm32_adjust()
1462 struct ptp_context *ptp_context = dev->data; in ptp_clock_stm32_rate_adjust()
1463 struct eth_stm32_hal_dev_data *eth_dev_data = ptp_context->eth_dev_data; in ptp_clock_stm32_rate_adjust()
1464 ETH_HandleTypeDef *heth = ð_dev_data->heth; in ptp_clock_stm32_rate_adjust()
1475 ratio *= (double)eth_dev_data->clk_ratio_adj; in ptp_clock_stm32_rate_adjust()
1480 ret = -EINVAL; in ptp_clock_stm32_rate_adjust()
1485 eth_dev_data->clk_ratio_adj = ratio; in ptp_clock_stm32_rate_adjust()
1488 addend_val = UINT32_MAX * (double)eth_dev_data->clk_ratio * ratio; in ptp_clock_stm32_rate_adjust()
1491 heth->Instance->MACTSAR = addend_val; in ptp_clock_stm32_rate_adjust()
1492 heth->Instance->MACTSCR |= ETH_MACTSCR_TSADDREG; in ptp_clock_stm32_rate_adjust()
1493 while (heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG_Msk) { in ptp_clock_stm32_rate_adjust()
1497 heth->Instance->PTPTSAR = addend_val; in ptp_clock_stm32_rate_adjust()
1498 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSARU; in ptp_clock_stm32_rate_adjust()
1499 while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU_Msk) { in ptp_clock_stm32_rate_adjust()
1522 struct eth_stm32_hal_dev_data *eth_dev_data = dev->data; in ptp_stm32_init()
1523 const struct eth_stm32_hal_dev_cfg *eth_cfg = dev->config; in ptp_stm32_init()
1524 struct ptp_context *ptp_context = port->data; in ptp_stm32_init()
1525 ETH_HandleTypeDef *heth = ð_dev_data->heth; in ptp_stm32_init()
1531 eth_dev_data->ptp_clock = port; in ptp_stm32_init()
1532 ptp_context->eth_dev_data = eth_dev_data; in ptp_stm32_init()
1536 heth->Instance->MACIER &= ~(ETH_MACIER_TSIE); in ptp_stm32_init()
1538 heth->Instance->MACIMR &= ~(ETH_MACIMR_TSTIM); in ptp_stm32_init()
1543 heth->Instance->MACTSCR |= ETH_MACTSCR_TSENA; in ptp_stm32_init()
1545 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSE; in ptp_stm32_init()
1549 ret = clock_control_get_rate(eth_dev_data->clock, in ptp_stm32_init()
1551 (clock_control_subsys_t)ð_cfg->pclken, in ptp_stm32_init()
1553 (clock_control_subsys_t)ð_cfg->pclken_ptp, in ptp_stm32_init()
1558 return -EIO; in ptp_stm32_init()
1564 return -EINVAL; in ptp_stm32_init()
1569 return -EINVAL; in ptp_stm32_init()
1572 heth->Instance->MACSSIR = ss_incr_ns << ETH_MACMACSSIR_SSINC_Pos; in ptp_stm32_init()
1574 heth->Instance->PTPSSIR = ss_incr_ns; in ptp_stm32_init()
1578 eth_dev_data->clk_ratio = in ptp_stm32_init()
1587 eth_dev_data->clk_ratio_adj = 1.0f; in ptp_stm32_init()
1589 UINT32_MAX * eth_dev_data->clk_ratio * eth_dev_data->clk_ratio_adj; in ptp_stm32_init()
1591 heth->Instance->MACTSAR = addend_val; in ptp_stm32_init()
1592 heth->Instance->MACTSCR |= ETH_MACTSCR_TSADDREG; in ptp_stm32_init()
1593 while (heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG_Msk) { in ptp_stm32_init()
1597 heth->Instance->PTPTSAR = addend_val; in ptp_stm32_init()
1598 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSARU; in ptp_stm32_init()
1599 while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU_Msk) { in ptp_stm32_init()
1606 heth->Instance->MACTSCR |= ETH_MACTSCR_TSCFUPDT; in ptp_stm32_init()
1608 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSFCU; in ptp_stm32_init()
1613 heth->Instance->MACTSCR |= ETH_MACTSCR_TSCTRLSSR; in ptp_stm32_init()
1615 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSSR; in ptp_stm32_init()
1620 heth->Instance->MACSTSUR = 0; in ptp_stm32_init()
1621 heth->Instance->MACSTNUR = 0; in ptp_stm32_init()
1622 heth->Instance->MACTSCR |= ETH_MACTSCR_TSINIT; in ptp_stm32_init()
1623 while (heth->Instance->MACTSCR & ETH_MACTSCR_TSINIT_Msk) { in ptp_stm32_init()
1627 heth->Instance->PTPTSHUR = 0; in ptp_stm32_init()
1628 heth->Instance->PTPTSLUR = 0; in ptp_stm32_init()
1629 heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSTI; in ptp_stm32_init()
1630 while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSSTI_Msk) { in ptp_stm32_init()
1637 heth->IsPtpConfigured = ETH_STM32_PTP_CONFIGURED; in ptp_stm32_init()