Lines Matching +full:0 +full:xa
11 /* All Banks, Offset 0xe: Bank Select Register */
12 #define BSR 0xe
13 #define BSR_BANK_MASK GENMASK(2, 0) /* Which bank is currently selected */
14 #define BSR_IDENTIFY 0x33
17 /* Bank 0, Offset 0x0: Transmit Control Register */
18 #define TCR 0x0
19 #define TCR_TXENA 0x0001 /* Enable/disable transmitter */
20 #define TCR_PAD_EN 0x0080 /* Pad TX frames to 64 bytes */
22 /* Bank 0, Offset 0x02: EPH status register */
23 #define EPHSR 0x2
24 #define EPHSR_TX_SUC 0x0001 /* Last TX was successful */
26 /* Bank 0, Offset 0x4: Receive Control Register */
27 #define RCR 0x4
28 #define RCR_PRMS 0x0002 /* Promiscuous mode */
29 #define RCR_RXEN 0x0100 /* Enable/disable receiver */
30 #define RCR_STRIP_CRC 0x0200 /* Strip CRC from RX packets */
31 #define RCR_SOFT_RST 0x8000 /* Software reset */
33 /* Bank0, Offset 0x6: Counter Register */
34 #define ECR 0x6
35 #define ECR_SNGLCOL_MASK GENMASK(3, 0) /* Single collisions */
40 /* Bank 0, Offset 0x8: Memory information register */
41 #define MIR 0x8
42 #define MIR_SIZE_MASK GENMASK(7, 0) /* Memory size (2k pages) */
45 /* bank 0, offset 0xa: receive/phy control register */
46 #define RPCR 0xa
47 #define RPCR_ANEG 0x0800 /* Put PHY in autonegotiation mode */
48 #define RPCR_DPLX 0x1000 /* Put PHY in full-duplex mode */
49 #define RPCR_SPEED 0x2000 /* Manual speed selection */
52 #define RPCR_LED_LINK_ANY 0x0 /* 10baseT or 100baseTX link detected */
53 #define RPCR_LED_LINK_10 0x2 /* 10baseT link detected */
54 #define RPCR_LED_LINK_FDX 0x3 /* Full-duplex link detect */
55 #define RPCR_LED_LINK_100 0x5 /* 100baseTX link detected */
56 #define RPCR_LED_ACT_ANY 0x4 /* TX or RX activity detected */
57 #define RPCR_LED_ACT_RX 0x6 /* RX activity detected */
58 #define RPCR_LED_ACT_TX 0x7 /* TX activity detected */
60 /* Bank 1, Offset 0x0: Configuration Register */
61 #define CR 0x0
62 #define CR_EPH_POWER_EN 0x8000 /* Disable/enable low power mode */
64 /* Bank 1, Offset 0x2: Base Address Register */
65 #define BAR 0x2
67 /* Bank 1, Offsets 0x4: Individual Address Registers */
68 #define IAR0 0x4
69 #define IAR1 0x5
70 #define IAR2 0x6
71 #define IAR3 0x7
72 #define IAR4 0x8
73 #define IAR5 0x9
75 /* Bank 1, Offset 0xc: Control Register */
76 #define CTR 0xc
77 #define CTR_LE_ENABLE 0x0080 /* Link error causes EPH interrupt */
78 #define CTR_AUTO_RELEASE 0x0800 /* Automatically release TX packets */
80 /* Bank 2, Offset 0x0: MMU Command Register */
81 #define MMUCR 0x0
82 #define MMUCR_BUSY 0x0001 /* MMU is busy */
90 /* Bank2, Offset 0x2: Packet Number Register */
91 #define PNR 0x2
92 #define PNR_MASK GENMASK(5, 0)
94 /* Bank2, Offset 0x3: Allocation Result Register */
95 #define ARR 0x3
96 #define ARR_FAILED 0x80
97 #define ARR_MASK GENMASK(5, 0)
99 /* Bank 2, Offset 0x4: FIFO Ports Register */
100 #define FIFO 0x04
101 #define FIFO_TX 0x4
102 #define FIFO_RX 0x5
103 #define FIFO_EMPTY 0x80 /* FIFO empty */
104 #define FIFO_PACKET_MASK GENMASK(5, 0) /* Packet number mask */
106 /* Bank2, Offset 0x6: Point Register */
107 #define PTR 0x6
108 #define PTR_MASK GENMASK(10, 0) /* Address accessible within TX/RX */
109 #define PTR_NOT_EMPTY 0x0800 /* Write Data FIFO not empty */
110 #define PTR_READ 0x2000 /* Set read/write */
111 #define PTR_AUTO_INCR 0x4000 /* Auto increment on read/write */
112 #define PTR_RCV 0x8000 /* Read/write to/from RX/TX */
114 /* Bank2, Offset 0x8: Data register */
115 #define DATA0 0x8
116 #define DATA1 0xa
118 /* Bank 2, Offset 0xc: Interrupt Status Registers */
119 #define IST 0xc /* read only */
120 #define ACK 0xc /* write only */
121 #define MSK 0xd
123 #define RCV_INT 0x0001 /* RX */
124 #define TX_INT 0x0002 /* TX */
125 #define TX_EMPTY_INT 0x0004 /* TX empty */
126 #define ALLOC_INT 0x0008 /* Allocation complete */
127 #define RX_OVRN_INT 0x0010 /* RX overrun */
128 #define EPH_INT 0x0020 /* EPH interrupt */
129 #define ERCV_INT 0x0040 /* Early RX */
130 #define MD_INT 0x0080 /* MII */
132 /* Bank 3, Offset 0x8: Management interface register */
133 #define MGMT 0x8
134 #define MGMT_MDO 0x0001 /* MII management output */
135 #define MGMT_MDI 0x0002 /* MII management input */
136 #define MGMT_MCLK 0x0004 /* MII management clock */
137 #define MGMT_MDOE 0x0008 /* MII management output enable */
139 /* Bank 3, Offset 0xa: Revision Register */
140 #define REV 0xa
142 #define REV_REV_MASK GENMASK(3, 0)
145 #define CTRL_CRC 0x10 /* Frame has CRC */
146 #define CTRL_ODD 0x20 /* Frame has odd bytes count */
149 #define RX_TOOSHORT 0x0400 /* Frame was too short */
150 #define RX_TOOLNG 0x0800 /* Frame was too long */
151 #define RX_ODDFRM 0x1000 /* Frame has odd number of bytes */
152 #define RX_BADCRC 0x2000 /* Frame failed CRC */
153 #define RX_ALIGNERR 0x8000 /* Frame has alignment error */
154 #define RX_LEN_MASK GENMASK(10, 0)